Electronics components

hardware design techniques 9.1 passive components chapter 9 hardware design techniques this chapter, one of the longer of those within the book, deals with topics just as important as all of those basic circuits immediately surrounding the data converter, discussed earlier. the chapter deals with various and sundry circuit/system issues which fall under the guise of system hardware design techniques. in this context, the design techniques may be all those support items surrounding a data converter, excluding the data converter itself. this includes issues of passive components, printed circuit design, power supply systems, protection of linear devices against overvoltage and thermal effects, emi/rfi issues, high speed logic considerations, and finally, simulation, breadboarding and prototyping. some of these topics aren't directly involved in the actual signal path of a design, but they are every bit as important as choosing the correct device and surrounding circuit values. remote sensing and signal conditioning is such a vital part of data conversion that a considerable amount of discussion is given to topics such as overvoltage protection, cable driving, shielding, and receiving—where the remote interface is often with op amps and instrumentation amplifiers. much of this material has been extracted from a companion publication by walter g. jung: op amp applications, analog devices, 2002. section 9.1: passive components james bryant, walt jung, walt kester introduction when designing with data converters, op amps, and other precision analog devices, it is critical that users avoid the pitfall of poor passive component choice. in fact, the wrong passive component can derail even the best op amp or data converter application. this section includes discussion of some basic traps of choosing passive components for op amp and data converter applications. so, you've spent good money for a precision op amp or data converter, only to find that, when plugged into your board, the device doesn't meet spec. perhaps the circuit suffers from drift, poor frequency response, and oscillations—or simply doesn't achieve expected accuracy. well, before you blame the device, you should closely examine your passive components—including capacitors, resistors, potentiometers, and yes, even the printed circuit boards. in these areas, subtle effects of tolerance, temperature, parasitics, aging, and user assembly procedures can unwittingly sink your circuit. and all too often these effects go unspecified (or underspecified) by passive component manufacturers. in general, if you use data converters having 12 bits or more of resolution, or op amps that cost more than a few dollars, pay very close attention to passive components. 9.1

analog-digital conversion consider the case of a 12-bit dac, where ½ lsb corresponds to 0.012% of full scale, or only 122 ppm. a host of passive component phenomena can accumulate errors far exceeding this! but, buying the most expensive passive components won't necessarily solve your problems either. often, a correct 25-cent capacitor yields a better-performing, more cost-effective design than a premium-grade part. with a few basics, understanding and analyzing passive components may prove rewarding, albeit not easy. capacitors most designers are generally familiar with the range of capacitors available. but the mechanisms by which both static and dynamic errors can occur in precision circuit designs using capacitors are sometimes easy to forget, because of the tremendous variety of types available. these include dielectrics of glass, aluminum foil, solid tantalum and tantalum foil, silver mica, ceramic, teflon, and the film capacitors, including polyester, polycarbonate, polystyrene, and polypropylene types. in addition to the traditional leaded packages, many of these are now also offered in surface mount styles. figure 9.1 is a workable model of a non-ideal capacitor. the nominal capacitance, c, is shunted by a resistance rp, which represents insulation resistance or leakage. a second resistance, rs—equivalent series resistance, or esr,—appears in series with the capacitor and represents the resistance of the capacitor leads and plates. r p c r da c da r s l (esr) (esl) figure 9.1: a non-ideal capacitor equivalent circuit includes parasitic elements note that capacitor phenomena aren't that easy to isolate. the matching of phenomena and models is for convenience in explanation. inductance, l—the equivalent series inductance, or esl—models the inductance of the leads and plates. finally, resistance rda and capacitance cda together form a simplified model of a phenomenon known as dielectric absorption, or da. it can ruin fast and slow circuit dynamic performance. in a real capacitor rda and cda extend to include multiple parallel sets. these parasitic rc elements can act to degrade timing circuits substantially, and the phenomenon is discussed further below. 9.2

hardware design techniques 9.1 passive components dielectric absorption dielectric absorption, which is also known as "soakage" and sometimes as "dielectric hysteresis"—is perhaps the least understood and potentially most damaging of various capacitor parasitic effects. upon discharge, most capacitors are reluctant to give up all of their former charge, due to this memory consequence. figure 9.2 illustrates this effect. on the left of the diagram, after being charged to the source potential of v volts at time to, the capacitor is shorted by the switch s1 at time t1, discharging it. at time t2, the capacitor is then open-circuited; a residual voltage slowly builds up across its terminals and reaches a nearly constant value. this error voltage is due to da, and is shown in the right figure, a time/voltage representation of the charge/discharge/recovery sequence. note that the recovered voltage error is proportional to both the original charging voltage v, as well as the rated da for the capacitor in use. t0 t1 s1 t2 v vo v c vo v x da t t0 t1 t2 figure 9.2: a residual open-circuit voltage after charge/discharge characterizes capacitor dielectric absorption standard techniques for specifying or measuring dielectric absorption are few and far between. measured results are usually expressed as the percentage of the original charging voltage that reappears across the capacitor. typically, the capacitor is charged for a long period, then shorted for a shorter established time. the capacitor is then allowed to recover for a specified period, and the residual voltage is then measured (see reference 8 for details). while this explanation describes the basic phenomenon, it is important to note that real-world capacitors vary quite widely in their susceptibility to this error, with their rated da ranging from well below to above 1%, the exact number being a function of the dielectric material used. in practice, da makes itself known in a variety of ways. perhaps an integrator refuses to reset to zero, a voltage-to-frequency converter exhibits unexpected nonlinearity, or a sample-hold amplifier (sha) exhibits varying errors. this last manifestation can be particularly damaging in a data-acquisition system, where adjacent channels may be at voltages which differ by nearly full scale, as shown below. figure 9.3 illustrates the case of da error in a simple sha. on the left, switches s1 and s2 represent an input multiplexer and sha switch, respectively. the multiplexer output voltage is vx, and the sampled voltage held on c is vy, which is buffered by the op amp for presentation to an adc. as can be noted by the timing diagram on the right, a da error voltage, ∈, appears in the hold mode, when the capacitor is effectively open circuit. 9.3

analog-digital conversion this voltage is proportional to the difference of voltages v1 and v2, which, if at opposite extremes of the dynamic range, exacerbates the error. as a practical matter, the best solution for good performance in terms of da in a sha is to use only the best capacitor. s1 s2 vy to adc v1 vy ∈ = (v1-v2) da vx v2 vx c open s2 closed v1 v2 v3 vn figure 9.3: dielectric absorption induces errors in sha applications the da phenomenon is a characteristic of the dielectric material itself, although inferior manufacturing processes or electrode materials can also affect it. da is specified as a percentage of the charging voltage. it can range from a low of 0.02% for teflon, polystyrene, and polypropylene capacitors, up to a high of 10% or more for some electrolytics. for some time frames, the da of polystyrene can be as low as 0.002%. common high-k ceramics and polycarbonate capacitor types display typical da on the order of 0.2%, it should be noted this corresponds to ½ lsb at only 8 bits! silver mica, glass, and tantalum capacitors typically exhibit even larger da, ranging from 1.0% to 5.0%, with those of polyester devices falling in the vicinity of 0.5%. as a rule, if the capacitor spec sheet doesn't specifically discuss da within your time frame and voltage range, exercise caution! another type with lower specified da is likely a better choice. da can produce long tails in the transient response of fast-settling circuits, such as those found in high-pass active filters or ac amplifiers. in some devices used for such applications, figure 9.1's rda-cda model of da can have a time constant of milliseconds. much longer time constants are also quite usual. in fact, several paralleled rda-cda circuit sections with a wide range of time constants can model some devices. in fast-charge, fast-discharge applications, the behavior of the da mechanism resembles "analog memory"; the capacitor in effect tries to remember its previous voltage. in some designs, you can compensate for the effects of da if it is simple and easily characterized, and you are willing to do custom tweaking. in an integrator, for instance, the output signal can be fed back through a suitable compensation network, tailored to cancel the circuit equivalent of the da by placing a negative impedance effectively in parallel. such compensation has been shown to improve sh circuit performance by factors of 10 or more (reference 6). 9.4

hardware design techniques 9.1 passive components capacitor parasitics and dissipation factor in figure 9.1, a capacitor's leakage resistance, rp, the effective series resistance, rs, and effective series inductance, l, act as parasitic elements, which can degrade an external circuit's performance. the effects of these elements are often lumped together and defined as a dissipation factor, or df. a capacitor's leakage is the small current that flows through the dielectric when a voltage is applied. although modeled as a simple insulation resistance (rp) in parallel with the capacitor, the leakage actually is nonlinear with voltage. manufacturers often specify leakage as a megohm-microfarad product, which describes the dielectric's self-discharge time constant, in seconds. it ranges from a low of 1 second or less for high-leakage capacitors, such as electrolytic devices, to the 100s of seconds for ceramic capacitors. glass devices exhibit self-discharge time-constants of 1,000 or more; but the best leakage performance is shown by teflon and the film devices (polystyrene, polypropylene), with time constants exceeding 1,000,000 megohm-microfarads. for such a device, external leakage paths—created by surface contamination of the device's case or in the associated wiring or physical assembly—can overshadow the internal dielectric-related leakage. effective series inductance, esl (figure 9.1, again) arises from the inductance of the capacitor leads and plates, which, particularly at the higher frequencies, can turn a capacitor's normally capacitive reactance into an inductive reactance. its magnitude strongly depends on construction details within the capacitor. tubular wrapped-foil devices display significantly more lead inductance than molded radial-lead configurations. multilayer ceramic (mlc) and film-type devices typically exhibit the lowest series inductance, while ordinary tantalum and aluminum electrolytics typically exhibit the highest. consequently, standard electrolytic types, if used alone, usually prove insufficient for high-speed local bypassing applications. note however that there also are more specialized aluminum and tantalum electrolytics available, which may be suitable for higher speed uses, however, localized bypassing is still recommended. these are the types generally designed for use in switch-mode power supplies, which are covered more completely in a following section. manufacturers of capacitors often specify effective series impedance by means of impedance-versus-frequency plots. not surprisingly, these curves show graphically a predominantly capacitive reactance at low frequencies, with rising impedance at higher frequencies because of the effect of series inductance. effective series resistance, esr (resistor rs of figure 9.1), is made up of the resistance of the leads and plates. as noted, many manufacturers lump the effects of esr, esl, and leakage into a single parameter called dissipation factor, or df. dissipation factor measures the basic inefficiency of the capacitor. manufacturers define it as the ratio of the energy lost to energy stored per cycle by the capacitor. the ratio of esr to total capacitive reactance—at a specified frequency—approximates the dissipation factor, which turns out to be equivalent to the reciprocal of the figure of merit, q. stated as an approximation, q ≈ 1/df (with df in numeric terms). for example, a df of 0.1% is equivalent to a fraction of 0.001; thus the inverse in terms of q would be 1000. 9.5

analog-digital conversion dissipation factor often varies as a function of both temperature and frequency. capacitors with mica and glass dielectrics generally have df values from 0.03% to 1.0%. for ceramic devices, df ranges from a low of 0.1 % to as high as 2.5% at room temperature. and electrolytics usually exceed even this level. the film capacitors are the best as a group, with dfs of less than 0.1 %. stable-dielectric ceramics, notably the np0 (also called cog) types, have df specs comparable to films (more below). tolerance, temperature, and other effects in general, precision capacitors are expensive and—even then—not necessarily easy to buy. in fact, choice of capacitance is limited both by the range of available values, and also by tolerances. in terms of size, the better performing capacitors in the film families tend to be limited in practical terms to 10 µf or less (for dual reasons of size and expense). in terms of low value tolerance, ±1% is possible for np0 ceramic and some film devices, but with possibly unacceptable delivery times. many film capacitors can be made available with tolerances of less than ±1%, but on a special order basis only. most capacitors are sensitive to temperature variations. df, da, and capacitance value are all functions of temperature. for some capacitors, these parameters vary approximately linearly with temperature, in others they vary quite nonlinearly. although it is usually not important for sha applications, an excessively large temperature coefficient (tc, measured in ppm/°c) can prove harmful to the performance of precision integrators, voltage-to-frequency converters, and oscillators. np0 ceramic capacitors, with tcs as low as 30 ppm/°c, are the best for stability, with polystyrene and polypropylene next best, with tcs in the 100-200 ppm/°c range. on the other hand, when capacitance stability is important, one should stay away from types with tcs of more than a few hundred ppm/°c, or in fact any tc which is nonlinear. a capacitor's maximum working temperature should also be considered, in light of the expected environment. polystyrene capacitors, for instance, melt near 85°c, compared to teflon's ability to survive temperatures up to 200°c. sensitivity of capacitance and da to applied voltage, expressed as voltage coefficient, can also hurt capacitor performance within a circuit application. although capacitor manufacturers don't always clearly specify voltage coefficients, the user should always consider the possible effects of such factors. for instance, when maximum voltages are applied, some high-k ceramic devices can experience a decrease in capacitance of 50% or more. this is an inherent distortion producer, making such types unsuitable for signal path filtering, for example, and better suited for supply bypassing. interestingly, np0 ceramics, the stable dielectric subset from the wide range of available ceramics, do offer good performance with respect to voltage coefficient. similarly, the capacitance and dissipation factor of many types vary significantly with frequency, mainly as a result of a variation in dielectric constant. in this regard, the better dielectrics are polystyrene, polypropylene, and teflon. 9.6

hardware design techniques 9.1 passive components assemble critical components last the designer's worries don't end with the design process. some common printed circuit assembly techniques can prove ruinous to even the best designs. for instance, some commonly used cleaning solvents can infiltrate certain electrolytic capacitors—those with rubber end caps are particularly susceptible. even worse, some of the film capacitors, polystyrene in particular, actually melt when contacted by some solvents. rough handling of the leads can damage still other capacitors, creating random or even intermittent circuit problems. etched-foil types are particularly delicate in this regard. to avoid these difficulties it may be advisable to mount especially critical components as the last step in the board assembly process—if possible. table 9.1 summarizes selection criteria for various capacitor types, arranged roughly in order of decreasing da performance. in a selection process, the general information of this table should be supplemented by consultation of current vendor's catalog information (see references at end of section). designers should also consider the natural failure mechanisms of capacitors. metallized film devices, for instance, often self-heal. they initially fail due to conductive bridges that develop through small perforations in the dielectric film. but, the resulting fault currents can generate sufficient heat to destroy the bridge, thus returning the capacitor to normal operation (at a slightly lower capacitance). of course, applications in high-impedance circuits may not develop sufficient current to clear the bridge, so the designer must be wary here. tantalum capacitors also exhibit a degree of self-healing, but—unlike film capacitors— the phenomenon depends on the temperature at the fault location rising slowly. therefore, tantalum capacitors self-heal best in high impedance circuits which limit the surge in current through the capacitor's defect. use caution therefore, when specifying tantalums for high-current applications. electrolytic capacitor life often depends on the rate at which capacitor fluids seep through end caps. epoxy end seals perform better than rubber seals, but an epoxy sealed capacitor can explode under severe reverse-voltage or overvoltage conditions. finally, all polarized capacitors must be protected from exposure to voltages outside their specifications. 9.7

hardware design techniques 9.1 passive components resistors and potentiometers designers have a broad range of resistor technologies to choose from, including carbon composition, carbon film, bulk metal, metal film, and both inductive and non-inductive wire-wound types. as perhaps the most basic—and presumably most trouble-free—of components, resistors are often overlooked as error sources in high performance circuits. yet, an improperly selected resistor can subvert the accuracy of a 12-bit design by developing errors well in excess of 122 ppm (½ lsb). when did you last read a resistor data sheet? you'd be surprised what can be learned from an informed review of data. + + _ _ g = 1 + g = 1 + r1 r1 r2 r2 = 100 = 100 r1 = 9.9kω, 1/4 w r1 = 9.9kω, 1/4 w tc = +25ppm/°c tc = +25ppm/°c r2 = 100ω, 1/4 w r2 = 100ω, 1/4 w tc = +50ppm/°c tc = +50ppm/°c (cid:139) temperature change of 10°c causes gain change of 250ppm (cid:139) temperature change of 10°c causes gain change of 250ppm (cid:139) this is 1lsb in a 12-bit system and a disaster in a 16-bit system (cid:139) this is 1lsb in a 12-bit system and a disaster in a 16-bit system figure 9.4: mismatched resistor tcs can induce temperature-related gain errors consider the simple circuit of figure 9.4, showing a non-inverting op amp where the 100× gain is set by r1 and r2. the tcs of these two resistors are a somewhat obvious source of error. assume the op amp gain errors to be negligible, and that the resistors are perfectly matched to a 99/1 ratio at +25ºc. if, as noted, the resistor tcs differ by only 25 ppm/ºc, the gain of the amplifier changes by 250 ppm for a 10ºc temperature change. this is about a 1 lsb error in a 12-bit system, and a major disaster in a 16-bit system. temperature changes, however, can limit the accuracy of the figure 9.4 amplifier in several ways. in this circuit (as well as many op amp circuits with component-ratio defined gains), the absolute tc of the resistors is less important—as long as they track one another in ratio. but even so, some resistor types simply aren't suitable for precise work. for example, carbon composition units—with tcs of approximately 1,500 ppm/°c, won't work. even if the tcs could be matched to an unlikely 1%, the resulting 15-ppm/°c differential still proves inadequate—an 8°c shift creates a 120-ppm error. many manufacturers offer metal film and bulk metal resistors, with absolute tcs ranging between ±1 and ±100 ppm/°c. beware, though; tcs can vary a great deal, particularly 9.9

analog-digital conversion among discrete resistors from different batches. to avoid this problem, more expensive matched resistor pairs are offered by some manufacturers, with temperature coefficients that track one another to within 2 to 10 ppm/°c. low-priced thin-film networks have good relative performance and are widely used. +100mv +100mv + + _ _ assume tc of r1 = tc of r2 assume tc of r1 = tc of r2 g = 1 + g = 1 + g = 1 + r1 r1 r1 r2 r2 r2 = 100 = 100 = 100 +10v +10v r1 = 9.9kω, 1/4 w r1 = 9.9kω, 1/4 w tc = +25ppm/°c tc = +25ppm/°c r2 = 100ω, 1/4 w r2 = 100ω, 1/4 w tc = +25ppm/°c tc = +25ppm/°c (cid:139) r1, r2 thermal resistance = 125°c / w (cid:139) r1, r2 thermal resistance = 125°c / w (cid:139) temperature of r1 will rise by 1.24°c, pd = 9.9mw (cid:139) temperature of r1 will rise by 1.24°c, pd = 9.9mw (cid:139) temperature rise of r2 is negligible, pd = 0.1mw (cid:139) temperature rise of r2 is negligible, pd = 0.1mw (cid:139) gain is altered by 31ppm, or 1/2 lsb @ 14-bits (cid:139) gain is altered by 31ppm, or 1/2 lsb @ 14-bits figure 9.5: uneven power dissipation between resistors with identical tcs can also introduce temperature-related gain errors suppose, as shown in figure 9.5, r1 and r2 are ¼w resistors with identical 25-ppm/ºc tcs. even when the tcs are identical, there can still be significant errors! when the signal input is zero, the resistors dissipate no heat. but, if it is 100 mv, there is 9.9 v across r1, which then dissipates 9.9 mw. it will experience a temperature rise of 1.24ºc (due to a 125ºc/w, ¼w resistor thermal resistance). this 1.24ºc rise causes a resistance change of 31 ppm, and thus a corresponding gain change. but r2, with only 100 mv across it, is only heated a negligible 0.0125ºc. the resulting 31-ppm net gain error represents a fullscale error of ½ lsb at 14-bits, and is a disaster for a 16-bit system. even worse, the effects of this resistor self-heating also create easily calculable nonlinearity errors. in the figure 9.5 example, with ½ the voltage input, the resulting self-heating error is only 15 ppm. in other words, the stage gain is not constant at ½ and full-scale (nor is it so at other points), as long as uneven temperature shifts exist between the gain-determining resistors. this is by no means a worst-case example; physically smaller resistors would give worse results, due to higher associated thermal resistance. these, and similar errors, are avoided by selecting critical resistors that are accurately matched for both value and tc, are well derated for power, and have tight thermal coupling between those resistors were matching is important. this is best achieved by using a resistor network on a single substrate—such a network may either be within an ic, or it may be a separately packaged thin-film resistor network. 9.10

hardware design techniques 9.1 passive components when the circuit resistances are very low (≤10 ω), interconnection stability also becomes important. for example, while often overlooked as an error, the resistance tc of typical copper wire or printed circuit traces can add errors. the tc of copper is typically ~3,900 ppm/°c. thus a precision 10-ω, 10-ppm/°c wirewound resistor with 0.1 ω of copper interconnect effectively becomes a 10.1-ω resistor with a tc of nearly 50 ppm/°c. one final consideration applies mainly to designs that see widely varying ambient temperatures: a phenomenon known as temperature retrace describes the change in resistance which occurs after a specified number of cycles of exposure to low and high ambients with constant internal dissipation. temperature retrace can exceed 10 ppm/°c, even for some of the better thin-film components. in summary, to design resistance-based circuits for minimum temperature-related errors, consider the points noted in figure 9.6 (along with their cost). (cid:139) closely match resistance tcs. (cid:139) use resistors with low absolute tcs. (cid:139) use resistors with low thermal resistance (higher power ratings, larger cases). (cid:139) tightly couple matched resistors thermally (use standard common- substrate networks). (cid:139) for large ratios consider using stepped attenuators. figure 9.6: a number of points are important towards minimizing temperature-related errors in resistors resistor parasitics resistors can exhibit significant levels of parasitic inductance or capacitance, especially at high frequencies. manufacturers often specify these parasitic effects as a reactance error, in % or ppm, based on the ratio of the difference between the impedance magnitude and the dc resistance, to the resistance, at one or more frequencies. wirewound resistors are especially susceptible to difficulties. although resistor manufacturers offer wirewound components in either normal or noninductively wound form, even noninductively wound resistors create headaches for designers. these resistors still appear slightly inductive (of the order of 20 µh) for values below 10 kω. above 10 kω the same style resistors actually exhibit 5 pf of shunt capacitance. these parasitic effects can raise havoc in dynamic circuit applications. of particular concern are applications using wirewound resistors with values greater than 10 kω. here it isn't uncommon to see peaking, or even oscillation. these effects become more evident at low-khz frequency ranges. 9.11

analog-digital conversion even in low-frequency circuit applications, parasitic effects in wirewound resistors can create difficulties. exponential settling to 1 ppm may take 20 time constants or more. the parasitic effects associated with wirewound resistors can significantly increase net circuit settling time to beyond the length of the basic time constants. unacceptable amounts of parasitic reactance are often found even in resistors that aren't wirewound. for instance, some metal-film types have significant interlead capacitance, which shows up at high frequencies. in contrast, when considering this end-to-end capacitance, carbon resistors do the best at high frequencies. thermoelectric effects another more subtle problem with resistors is the thermocouple effect, also sometimes referred to as thermal emf. wherever there is a junction between two different metallic conductors, a thermoelectric voltage results. the thermocouple effect is widely used to measure temperature. however, in any low level precision op amp circuit it is also a potential source of inaccuracy, since wherever two different conductors meet, a thermocouple is formed (whether we like it or not). in fact, in many cases, it can easily produce the dominant error within an otherwise precision circuit design. parasitic thermocouples will cause errors when and if the various junctions forming the parasitic thermocouples are at different temperatures. with two junctions present on each side of the signal being processed within a circuit, by definition we have formed at least one thermocouple pair. if the two junctions of this thermocouple pair are at different temperatures, there will be a net temperature dependent error voltage produced. conversely, if the two junctions of a parasitic thermocouple pair are kept at an identical temperature, then the net error produced will be zero, as the voltages of the two thermocouples effectively will be canceled. this is a critically important point, since in practice we cannot avoid connecting dissimilar metals together to build an electronic circuit. but, what we can do is carefully control temperature differentials across the circuit, so such that the undesired thermocouple errors cancel one another. the effect of such parasitics is very hard to avoid. to understand this, consider a case of making connections with copper wire only. in this case, even a junction formed by different copper wire alloys can have a thermoelectric voltage which is a small fraction of 1 µv/ºc! and, taking things a step further, even such apparently benign components as resistors contain parasitic thermocouples, with potentially even stronger effects. for example, consider the resistor model shown in figure 9.7. the two connections between the resistor material and the leads form thermocouple junctions, t1 and t2. this thermocouple emf can be as high as 400 µv/ºc for some carbon composition resistors, and as low as 0.05 µv/ºc for specially constructed resistors (see reference 15). ordinary metal film resistors (rn-types) are typically about 20 µv/ºc. 9.12

hardware design techniques 9.1 passive components ++ t1 resistor material ++ + t2 resistor leads typical resistor thermocouple emfs (cid:139) carbon composition ≈ 400 µv/ °c (cid:139) metal film (cid:139) evenohm or manganin wirewound ≈ 20 µv/ °c ≈ 2 µv/ °c (cid:139) rcd components hp-series ≈ 0.05 µv/ °c figure 9.7: every resistor contains two thermocouples, formed between the leads and resistance element note that these thermocouple effects are relatively unimportant for ac signals. even for dc-only signals, they will nicely cancel one another, if, as noted above, the entire resistor is at a uniform temperature. however, if there is significant power dissipation in a resistor, or if its orientation with respect to a heat source is non-symmetrical, this can cause one of its ends to be warmer than the other, causing a net thermocouple error voltage. using ordinary metal film resistors, an end-to-end temperature differential of 1ºc causes a thermocouple voltage of about 20 µv. this error level is quite significant compared to the offset voltage drift of a precision op amp like the op177, and extremely significant when compared to chopper-stabilized op amps, with their drifts of <1 µv/°c. ∆t ∆t wrong wrong right right figure 9.8: the effects of thermocouple emfs generated by resistors can be minimized by orientation that equalizes the end temperatures figure 9.8 shows how resistor orientation can make a difference in the net thermocouple voltage. in the left diagram, standing the resistor on end in order to conserve board space will invariably cause a temperature gradient across the resistor, especially if it is dissipating any significant power. in contrast, placing the resistor flat on the pc board as shown at the right will generally eliminate the gradient. an exception might occur, if 9.13

analog-digital conversion there is end-to-end resistor airflow. for such cases, orienting the resistor axis perpendicular to the airflow will minimize this source of error, since this tends to force the resistor ends to the same temperature. note that this line of thinking should be extended, to include orientation of resistors on a vertically mounted pc board. in such cases, natural convection air currents tend to flow upward across the board. again, the resistor thermal axis should be perpendicular to convection, to minimize thermocouple effects. with tiny surface mount resistors, the thermocouple effects can be less problematic, due to tighter thermal coupling between the resistor ends. in general, designers should strive to avoid thermal gradients on or around critical circuit boards. often this means thermally isolating components that dissipate significant amounts of power. thermal turbulence created by large temperature gradients can also result in dynamic noise-like low-frequency errors. voltage sensitivity, failure mechanisms, and aging resistors are also plagued by changes in value as a function of applied voltage. the deposited-oxide high-megohm type components are especially sensitive, with voltage coefficients ranging from 1 ppm/v to more than 200 ppm/v. this is another reason to exercise caution in such precision applications as high-voltage dividers. the normal failure mechanism of a resistor can also create circuit difficulties, if not carefully considered beforehand. for example, carbon-composition resistors fail safely, by turning into open circuits. consequently, in some applications, these components can play a useful secondary role, as a fuse. replacing such a resistor with a carbon-film type can possibly lead to trouble, since carbon-films can fail as short circuits. (metal-film components usually fail as open circuits.) all resistors tend to change slightly in value with age. manufacturers specify long-term stability in terms of change—ppm/year. values of 50 or 75 ppm/year are not uncommon among metal film resistors. for critical applications, metal-film devices should be burned-in for at least one week at rated power. during burn-in, resistance values can shift by up to 100 or 200 ppm. metal film resistors may need 4-5000 operational hours for full stabilization, especially if deprived of a burn-in period. resistor excess noise most designers have some familiarity with thermal, or johnson noise, which occurs in resistors. but a less widely recognized secondary noise phenomenon is associated with resistors, and it is called excess noise. it can prove particularly troublesome in precision op amp and converter circuits, as it is evident only when current passes through a resistor. to review briefly, thermal noise results from thermally induced random vibration of charge resistor carriers. although the average current from the vibrations remains zero, instantaneous charge motions result in an instantaneous voltage across the terminals. 9.14

hardware design techniques 9.1 passive components excess noise on the other hand, occurs primarily when dc flows in a discontinuous medium—for example the conductive particles of a carbon composition resistor. the current flows unevenly through the compressed carbon granules, creating microscopic particle-to-particle "arcing". this phenomenon gives rise to a 1/f noise-power spectrum, in addition to the thermal noise spectrum. in other words, the excess spot noise voltage increases as the inverse square-root of frequency. excess noise often surprises the unwary designer. resistor thermal noise and op amp input noise set the noise floor in typical op amp circuits. only when voltages appear across input resistors and causes current to flow does the excess noise become a significant—and often dominant—factor. in general, carbon composition resistors generate the most excess noise. as the conductive medium becomes more uniform, excess noise becomes less significant. carbon film resistors do better, with metal film, wirewound and bulk-metal-film resistors doing better yet. manufacturers specify excess noise in terms of a noise index—the number of microvolts of rms noise in the resistor in each decade of frequency per volt of dc drop across the resistor. the index can rise to 10 db (3 microvolts per dc volt per decade of bandwidth) or more. excess noise is most significant at low frequencies, while above 100 khz thermal noise predominates. potentiometers trimming potentiometers (trimpots) can suffer from most of the phenomena that plague fixed resistors. in addition, users must also remain vigilant against some hazards unique to these components. for instance, many trimpots aren't sealed, and can be severely damaged by board washing solvents, and even by excessive humidity. vibration—or simply extensive use—can damage the resistive element and wiper terminations. contact noise, tcs, parasitic effects, and limitations on adjustable range can all hamper trimpot circuit operation. furthermore, the limited resolution of wirewound types and the hidden limits to resolution in cermet and plastic types (hysteresis, incompatible material tcs, slack) make obtaining and maintaining precise circuit settings anything but an "infinite resolution" process. given this background, two rules are suggested for the potential trimpot user. rule 1: use infinite care and infinitesimal adjustment range to avoid infinite frustration when applying manual trimpots. rule 2: consider the elimination of manual trimming potentiometers altogether, if possible! a number of digitally addressable potentiometers (rdacs or trimdacs®) are now available for direct application in similar circuit functions as classic trimpots (see reference 17). there are also many low cost multi- channel voltage output dacs expressly designed for system voltage trimming. table 9.2 summarizes selection criteria for various fixed resistor types, both in discrete form and as part of networks. in a selection process, the general information of this table should be supplemented by consultation of current vendor's catalog information (see references at end of section). 9.15

hardware design techniques 9.1 passive components inductance stray inductance all conductors are inductive, and at high frequencies, the inductance of even quite short pieces of wire or printed circuit traces may be important. the inductance of a straight wire of length l mm and circular cross-section with radius r mm in free space is given by the first equation shown in figure 9.9. 2r l, r in mm l wire inductance = 0.0002l ln - 0.75 h µ ( 2l r ) example: 1cm of 0.5mm o.d. wire has an inductance of 7.26nh (2r = 0.5mm, l = 1cm) l w h strip inductance = 0.0002l ln + 0.2235 + 0.5 µh ( 2l ( w+h ) w+h ) l example: 1cm of 0.25 mm pc track has an inductance of 9.59 nh (h = 0.038mm, w = 0.25mm, l = 1cm) figure 9.9: wire and strip inductance calculations the inductance of a strip conductor (an approximation to a pc track) of width w mm and thickness h mm in free space is also given by the second equation in figure 9.9. in real systems, both these formulas turn out to be approximate, but they do give some idea of the order of magnitude of inductance involved. they tell us that 1 cm of 0.5-mm od wire has an inductance of 7.26 nh, and 1 cm of 0.25-mm pc track has an inductance of 9.59 nh—these figures are reasonably close to measured results. at 10 mhz, an inductance of 7.26 nh has an impedance of 0.46 ω, and so can give rise to 1% error in a 50-ω system. mutual inductance another consideration regarding inductance is the separation of outward and return currents. kirchoff's law tells us that current flows in closed paths—there is always an outward and return path. the whole path forms a single-turn inductor. this principle is illustrated by the contrasting signal trace routing arrangements of figure 9.10. if the area enclosed within the turn is relatively large, as in the upper "nonideal" picture, then the inductance (and hence the ac impedance) will also be large. on the other 9.17

analog-digital conversion shielding of magnetic fields to reduce mutual inductance is sometimes possible, but is by no means as easy as shielding an electric field with a faraday shield (following section). hf magnetic fields are blocked by conductive material provided the skin depth in the conductor at the frequency to be screened is much less than the thickness of the conductor, and the screen has no holes (faraday shields can tolerate small holes, magnetic screens cannot). lf and dc fields may be screened by a shield made of mu- metal sheet. mu-metal is an alloy having very high permeability, but it is expensive, its magnetic properties are damaged by mechanical stress, and it will saturate if exposed to too high fields. its use, therefore, should be avoided where possible. ringing an inductor in series or parallel with a capacitor forms a resonant, or "tuned", circuit, whose key feature is that it shows marked change in impedance over a small range of frequency. just how sharp the effect is depends on the relative q of the tuned circuit. the effect is widely used to define the frequency response of narrow-band circuitry, but can also be a potential problem source. if stray inductance and capacitance (which may or may not be stray) in a circuit should form a tuned circuit, then that tuned circuit may be excited by signals in the circuit, and ring at its resonant frequency. an example is shown in figure 9.14, where the resonant circuit formed by an inductive power line and its decoupling capacitor may possibly be excited by fast pulse currents drawn by the powered ic. ic +vs l1 1µh ic c1 0.1µf r1 l1 +vs 1µh 10ω c1 0.1µf equivalent decoupled power line circuit resonates at: small series resistance close to ic reduces q f = f = 1 1 2π lc√ 2π lc√ figure 9.14: resonant circuit formed by power line decoupling while normal trace inductance and typical decoupling capacitances of 0.01-0.1µf will resonate well above a few mhz, an example 0.1-µf capacitor and 1 µh of inductance resonates at 500 khz. left unchecked, this could present a resonance problem, as shown in the left case. should an undesired power line resonance be present, the effect may be minimized by lowering the q of the inductance. this is most easily done by inserting a small resistance (~10 ω) in the power line close to the ic, as shown in the right case. 9.20

hardware design techniques 9.1 passive components parasitic effects in inductors although inductance is one of the fundamental properties of an electronic circuit, inductors are far less common as components than are resistors and capacitors. as for precision components, they are even more rare. this is because they are harder to manufacture, less stable, and less physically robust than resistors and capacitors. it is relatively easy to manufacture stable precision inductors with inductances from nh to tens or hundreds of µh, but larger valued devices tend to be less stable, and large. as we might expect in these circumstances, circuits are designed, where possible, to avoid the use of precision inductors. we find that stable precision inductors are rarely used in precision analog circuitry, except in tuned circuits for high frequency narrow band applications. of course, they are widely used in power filters, switching power supplies and other applications where lack of precision is unimportant (more on this in a following section). the important features of inductors used in such applications are their current carrying and saturation characteristics, and their q. if an inductor consists of a coil of wire with an air core, its inductance will be essentially unaffected by the current it is carrying. on the other hand, if it is wound on a core of a magnetic material (magnetic alloy or ferrite), its inductance will be non-linear, since at high currents, the core will start to saturate. the effects of such saturation will reduce the efficiency of the circuitry employing the inductor and is liable to increase noise and harmonic generation. as mentioned above, inductors and capacitors together form tuned circuits. since all inductors will also have some stray capacity, all inductors will have a resonant frequency (which will normally be published on their data sheet), and should only be used as precision inductors at frequencies well below this. q or "quality factor" the other characteristic of inductors is their q (or "quality factor"), which is the ratio of the reactive impedance to the resistance, as indicated in figure 9.15. (cid:139) q = 2πf l/r (cid:139) the q of an inductor or resonant circuit is a measure of the ratio of its reactance to its resistance. (cid:139) the resistance is the hf and not the dc value. (cid:139) the 3 db bandwidth of a single tuned circuit is fc/q where fc is the center frequency. figure 9.15: inductor q or quality factor 9.21

analog-digital conversion it is rarely possible to calculate the q of an inductor from its dc resistance, since skin effect (and core losses if the inductor has a magnetic core) ensure that the q of an inductor at high frequencies is always lower than that predicted from dc values. q is also a characteristic of tuned circuits (and of capacitors—but capacitors generally have such high q values that it may be disregarded, in practice). the q of a tuned circuit, which is generally very similar to the q of its inductor (unless it is deliberately lowered by the use of an additional resistor), is a measure of its bandwidth around resonance. lc tuned circuits rarely have q of much more than 100 (3-db bandwidth of 1%), but ceramic resonators may have a q of thousands, and quartz crystals tens of thousands. don't overlook anything remember, if your precision op amp or data-converter-based design does not meet specification, try not to overlook anything in your efforts to find the error sources. analyze both active and passive components, trying to identify and challenge any assumptions or preconceived notions that may blind you to the facts. take nothing for granted. for example, when not tied down to prevent motion, cable conductors, moving within their surrounding dielectrics, can create significant static charge buildups that cause errors, especially when connected to high-impedance circuits. rigid cables, or even costly low-noise teflon-insulated cables, are expensive alternative solutions. as more and more high-precision op amps become available, and system designs call for higher speed and increased accuracy, a thorough understanding of the error sources described in this section (as well those following) becomes more important. some additional discussions of passive components within a succeeding power supply filtering section complements this one. in addition, the very next section on pcb design issues also complements many points within this section. similar comments apply to the section on emi/rfi. 9.22

hardware design techniques 9.1 passive components references: 9.1 passive components 1. james e. buchanan, "dielectric absorption— it can be a real problem in timing circuits," edn, january 20, 1977, p 83. 2. lew counts and scott wurcer, "instrumentation amplifier nears input noise floor," electronic design, june 10, 1982. 3. w. doeling, w. mark, t. tadewald, and p. reichenbacher, "getting rid of hook: the hidden pc-board capacitance," electronics, october 12, 1978, p 111-117. 4. tarlton fleming, "data-acquisition system (das) design considerations," wescon '81 professional program session record no. 23. 5. walter g. jung and richard marsh, "picking capacitors, parts i and ii," audio, february and march, 1980. 6. robert a. pease, "understand capacitor soakage to optimize analog systems", edn, october 13, 1982, page 125. 7. andy rappaport, "capacitors" edn, october 13, 1982, page 105. 8. specification mil-prf-19978g, capacitors, fixed, plastic (or paper-plastic) dielectric (hermetically sealed in metal, ceramic or glass cases), established and non-established reliability general specification for, may 27, 1999. 9. specification mil-prf-123b, capacitors, fixed, ceramic dielectric, (temperature stable and general purpose), high reliability, general specification for, august 6, 1990. 10. tantalum and ceramic surface mount capacitor catalog, kemet electronics corporation, p.o. box 5928, greenville, sc, 29606, 864-963-6300. 11. a general capacitor information resource: http://www.faradnet.com/ 12. southern and f-dyne film capacitors, southern electronics, 215 research drive, milford, ct, 06460, 203-876-7488. 13. wesco film capacitors, wesco electrical company, 201 munson street, greenfield, ma, 01301, 413- 774-4358. 14. doug grant and scott wurcer, "avoiding passive component pitfalls," the best of analog dialogue, analog devices, 1991, p. 143-148. 15. rcd components, inc., 520 e. industrial park drive, manchester nh, 03109, 603-669-0054, http://www.rcd-comp.com 16. steve sockolov and james wong, "high-accuracy analog needs more than op amps," electronic design, october 1, 1992, p.53. 17. selection guide for digital potentiometers: http://www.analog.com/digitalpots 18. precision resistor co., inc., 10601 75th st. n., largo, fl, 33777-1427, 727 541-5771, http://www.precisionresistor.com 19. ohmite victoreen maxi-mox resistors, 3601 howard street, skokie, il 60076, 847 675-2600, http://www.ohmite.com/victoreen/. 9.23

hardware design techniques 9.2 pc board design issues section 9.2: pc board design issues james bryant, walt kester, walt jung printed circuit boards (pcbs) are by far the most common method of assembling modern electronic circuits. comprised of a sandwich of insulating layer (or layers) and one or more copper conductor patterns, they can introduce various forms of errors into a circuit, particularly if the circuit is operating at either high precision or high speed. pcbs then, act as "unseen" components, wherever they are used in precision circuit designs. since designers don’t always consider the pcb electrical characteristics as additional components of their circuit, overall performance can easily end up worse than predicted. this general topic, manifested in many forms, is the focus of this section. pcb effects that are harmful to precision circuit performance include leakage resistances; spurious voltage drops in trace foils, vias, and ground planes; the influence of stray capacitance, dielectric absorption (da), and the related "hook." in addition, the tendency of pcbs to absorb atmospheric moisture, hygroscopicity, means that changes in humidity often cause the contributions of some parasitic effects to vary from day to day. in general, pcb effects can be divided into two broad categories— those that most noticeably affect the static or dc operation of the circuit, and those that most noticeably affect dynamic or ac circuit operation. another very broad area of pcb design is the topic of grounding. grounding is a problem area in itself for all analog designs, and it can be said that implementing a pcb based circuit doesn't change that fact. fortunately, certain principles of quality grounding, namely the use of ground planes, are intrinsic to the pcb environment. this factor is one of the more significant advantages to pcb based analog designs, and an appreciable amount of this section is focused on this issue. some other aspects of grounding that must be managed include the control of spurious ground and signal return voltages that can degrade performance. these voltages can be due to external signal coupling, common currents, or simply excessive ir drops in ground conductors. proper conductor routing and sizing, as well as differential signal handling and ground isolation techniques enables control of such parasitic voltages. one final area of grounding to be discussed is grounding appropriate for a mixed-signal, analog/digital environment. this topic is the subject of many application calls, and it is certainly true that interfacing with adcs (or dacs) is a major part of the system design, and thus it shouldn't be overlooked. indeed, the single issue of quality grounding can drive the entire layout philosophy of a high performance mixed signal pcb design— as it well should. 9.25

analog-digital conversion resistance of conductors every engineer is familiar with resistors, although perhaps fewer are aware of their idiosyncrasies, as generally covered in section 9.1. but far too few engineers consider that all the wires and pcb traces with which their systems and circuits are assembled are also resistors. in higher precision systems, even these trace resistances and simple wire interconnections can have degrading effects. copper is not a superconductor—and too many engineers appear to think it is! figure 9.16 illustrates a method of calculating the sheet resistance r of a copper square, given the length z, the width x, and the thickness y. z ρ x r = ρ = resistivity y r z y x sheet resistance calculation for 1 oz. copper conductor: ρ = 1.724 x 10–6 ω cm, y = 0.0036cm r = 0.48 m ω z x z x = number of squares r = sheet resistance of 1 square (z=x) = 0.48m ω/square figure 9.16: calculation of sheet resistance and linear resistance for standard copper pcb conductors at 25°c the resistivity of pure copper is 1.724×10–6 ωcm. the thickness of standard 1 ounce pcb copper foil is 0.036 mm (0.0014"). using the relations shown, the resistance of such a standard copper element is therefore 0.48 mω /square. one can readily calculate the resistance of a linear trace, by effectively "stacking" a series of such squares end-end, to make up the line's length. the line length is z and the width is x, so the line resistance r is simply a product of z/x and the resistance of a single square, as noted in the figure. for a given copper weight and trace width, a resistance/length calculation can be made. for example, the 0.25-mm (10-mil) wide traces frequently used in pcb designs equates to a resistance/length of about 19 mω/cm (48 mω /inch), which is quite large. moreover, the temperature coefficient of resistance for copper is about 0.4% /°c around room temperature. this is a factor that shouldn't be ignored, in particular within low impedance precision circuits, where the tc can shift the net impedance over temperature. 9.26

hardware design techniques 9.2 pc board design issues as shown in figure 9.17, pcb trace resistance can be a serious error when conditions aren't favorable. consider a 16-bit adc with a 5-kω input resistance, driven through 5 cm of 0.25-mm wide 1-oz pcb track between it and its signal source. the track resistance of nearly 0.1 ω forms a divider with the 5-kω load, creating an error. the resulting voltage drop is a gain error of 0.1/5000 (~0.0019%), well over 1 lsb (0.0015% for 16 bits). 5cm signal source 16-bit adc, rin = 5kω 0.25mm (10 mils) wide, 1 oz. copper pcb trace assume ground path resistance negligible figure 9.17: ohm’s law predicts >1 lsb of error due to drop in pcb conductor so, when dealing with precision circuits, the point is made that even simple design items such as pcb trace resistance cannot be dealt with casually. there are various solutions that can address this issue, such as wider traces (which may take up excessive space), the use of heavier copper (which may be too expensive), or simply choosing a high impedance converter. but, the most important thing is to think it all through, avoiding any tendency to overlook items appearing innocuous on the surface. voltage drop in signal leads—"kelvin" feedback the gain error resulting from resistive voltage drop in pcb signal leads is important only with high precision and/or at high resolutions (the figure 9.17 example), or where large signal currents flow. where load impedance is constant and resistive, adjusting overall system gain can compensate for the error. in other circumstances, it may often be removed by the use of "kelvin" or "voltage sensing" feedback, as shown in figure 9.18. feedback "sense" lead signal source high resistance signal lead s f adc with low rin assume ground path resistance negligible figure 9.18: use of a sense connection moves accuracy to the load point 9.27

analog-digital conversion in this modification to the case of figure 9.17, a long resistive pcb trace is still used to drive the input of a high resolution adc, with low input impedance. in this case however, the voltage drop in the signal lead does not give rise to an error, as feedback is taken directly from the input pin of the adc, and returned to the driving source. this scheme allows full accuracy to be achieved in the signal presented to the adc, despite any voltage drop across the signal trace. the use of separate force (f) and sense (s) connections at the load removes any errors resulting from voltage drops in the force lead, but, of course, may only be used in systems where there is negative feedback. it is also impossible to use such an arrangement to drive two or more loads with equal accuracy, since feedback may only be taken from one point. also, in this much-simplified system, errors in the common lead source/load path are ignored, the assumption being that ground path voltages are negligible. in many systems this may not necessarily be the case, and additional steps may be needed, as noted below. signal return currents kirchoff's law tells us that at any point in a circuit the algebraic sum of the currents is zero. this tells us that all currents flow in circles and, particularly, that the return current must always be considered when analyzing a circuit, as is illustrated in figure 9.19 (see references 7 and 8). signal source i load rl ii g1 ground return current i g2 at any point in a circuit the algebraic sum of the currents is zero or what goes out must come back which leads to the conclusion that all voltages are differential (even if they’re grounded) figure 9.19: kirchoff’s law helps in analyzing voltage drops around a complete source/load coupled circuit in dealing with grounding issues, common human tendencies provide some insight into how the correct thinking about the circuit can be helpful towards analysis. most engineers readily consider the ground return current, "i", when they are considering a fully differential circuit. however, when considering the more usual circuit case, where a single-ended signal is referred to "ground", it is common to assume that all the points on the circuit diagram 9.28

hardware design techniques 9.2 pc board design issues where ground symbols are found are at the same potential. unfortunately, this happy circumstance just ain't necessarily so! this overly optimistic approach is illustrated in figure 9.20, where, if it really should exist, "infinite ground conductivity" would lead to zero ground voltage difference between source ground g1 and load ground g2. unfortunately this approach isn’t a wise practice, and when dealing with high precision circuits, it can lead to disasters. signal source g1 signal adc infinite ground conductivity → zero voltage differential between g1 & g2 g2 figure 9.20: unlike this optimistic diagram, it is unrealistic to assume infinite conductivity between source/load grounds in a real-world system a more realistic approach to ground conductor integrity includes analysis of the impedance(s) involved, and careful attention to minimizing spurious noise voltages. a more realistic model of a ground system is shown in figure 9.21. the signal return current flows in the complex impedance existing between ground points g1 and g2 as shown, giving rise to a voltage drop ∆v in this path. but it is important to note that additional external currents, such as iext, may also flow in this same path. it is critical to understand that such currents may generate uncorrelated noise voltages between g1 and g2 (dependent upon the current magnitude and relative ground impedance). signal signal source load isig ∆v = voltage differential due to signal current and/or external current flowing in ground impedance g1 g2 iext iext figure 9.21: a more realistic source-to-load grounding system view includes consideration of the impedance between g1-g2, plus the effect of any non- signal-related currents 9.29

analog-digital conversion some portion of these undesired voltages may end up being seen at the signal's load end, and they can have the potential to corrupt the signal being transmitted. grounding in mixed analog/digital systems walt kester, james bryant, mike byrne today's signal processing systems generally require mixed-signal devices such as analog- to-digital converters (adcs) and digital-to-analog converters (dacs) as well as fast digital signal processors (dsps). requirements for processing analog signals having wide dynamic ranges increases the importance of high performance adcs and dacs. maintaining wide dynamic range with low noise in hostile digital environments is dependent upon using good high-speed circuit design techniques including proper signal routing, decoupling, and grounding. in the past, "high precision, low-speed" circuits have generally been viewed differently than so-called "high-speed" circuits. with respect to adcs and dacs, the sampling (or update) frequency has generally been used as the distinguishing speed criteria. however, the following two examples show that in practice, most of today's signal processing ics are really "high-speed," and must therefore be treated as such in order to maintain high performance. this is certainly true of dsps, and also true of adcs and dacs. all sampling adcs (adcs with an internal sample-and-hold circuit) suitable for signal processing applications operate with relatively high speed clocks with fast rise and fall times (generally a few nanoseconds) and must be treated as high speed devices, even though throughput rates may appear low. for example, a medium-speed 12-bit successive approximation (sar) adc may operate on a 10-mhz internal clock, while the sampling rate is only 500 ksps. sigma-delta (σ-∆) adcs also require high speed clocks because of their high oversampling ratios. even high resolution, so-called "low frequency" σ-∆ industrial measurement adcs (having throughputs of 10 hz to 7.5 khz) operate on 5-mhz or higher clocks and offer resolution to 24-bits (for example, the analog devices ad77xx- series). to further complicate the issue, mixed-signal ics have both analog and digital ports, and because of this, much confusion has resulted with respect to proper grounding techniques. in addition, some mixed-signal ics have relatively low digital currents, while others have high digital currents. in many cases, these two types must be treated differently with respect to optimum grounding. digital and analog design engineers tend to view mixed-signal devices from different perspectives, and the purpose of this section is to develop a general grounding philosophy that will work for most mixed signal devices, without having to know the specific details of their internal circuits. ground and power planes the importance of maintaining a low impedance large area ground plane is critical to all analog circuits today. the ground plane not only acts as a low impedance return path for 9.30

hardware design techniques 9.2 pc board design issues decoupling high frequency currents (caused by fast digital logic) but also minimizes emi/rfi emissions. because of the shielding action of the ground plane, the circuit's susceptibility to external emi/rfi is also reduced. ground planes also allow the transmission of high speed digital or analog signals using transmission line techniques (microstrip or stripline) where controlled impedances are required. the use of "buss wire" is totally unacceptable as a "ground" because of its impedance at the equivalent frequency of most logic transitions. for instance, #22 gauge wire has about 20 nh/inch inductance. a transient current having a slew rate of 10 ma/ns created by a logic signal would develop an unwanted voltage drop of 200 mv at this frequency flowing through 1 inch of this wire: =∆ lv ∆ i ∆ t = nh20 × 10 ma ns = 200 .mv eq. 9.1 for a signal having a 2-v peak-to-peak range, this translates into an error of about 200 mv, or 10% (approximate 3.5-bit accuracy). even in all-digital circuits, this error would result in considerable degradation of logic noise margins. figure 9.22 shows an illustration of a situation where the digital return current modulates the analog return current (top figure). the ground return wire inductance and resistance is shared between the analog and digital circuits, and this is what causes the interaction and resulting error. a possible solution is to make the digital return current path flow directly to the gnd ref as shown in the bottom figure. this is the fundamental concept of a "star," or single-point ground system. implementing the true single-point ground in a system which contains multiple high frequency return paths is difficult because the physical length of the individual return current wires will introduce parasitic resistance and inductance which can make obtaining a low impedance high frequency ground difficult. in practice, the current returns must consist of large area ground planes for low impedance to high frequency currents. without a low-impedance ground plane, it is therefore almost impossible to avoid these shared impedances, especially at high frequencies. all integrated circuit ground pins should be soldered directly to the low-impedance ground plane to minimize series inductance and resistance. the use of traditional ic sockets is not recommended with high-speed devices. the extra inductance and capacitance of even "low profile" sockets may corrupt the device performance by introducing unwanted shared paths. if sockets must be used with dip packages, as in prototyping, individual "pin sockets" or "cage jacks" may be acceptable. both capped and uncapped versions of these pin sockets are available (amp part numbers 5-330808-3, and 5-330808-6). they have spring-loaded gold contacts which make good electrical and mechanical connection to the ic pins. multiple insertions, however, may degrade their performance. 9.31

analog-digital conversion + + vd va gnd ref + vd + va gnd ref vin vin id ia incorrect analog circuits digital circuits ia + id id id ia correct analog circuits digital circuits ia id figure 9.22: digital currents flowing in analog return path create error voltages power supply pins should be decoupled directly to the ground plane using low inductance ceramic surface mount capacitors. if through-hole mounted ceramic capacitors must be used, their leads should be less than 1 mm. the ceramic capacitors should be located as close as possible to the ic power pins. ferrite beads may be also required for additional decoupling. double-sided vs. multilayer printed circuit boards each pcb in the system should have at least one complete layer dedicated to the ground plane. ideally, a double-sided board should have one side completely dedicated to ground and the other side for interconnections. in practice, this is not possible, since some of the ground plane will certainly have to be removed to allow for signal and power crossovers, vias, and through-holes. nevertheless, as much area as possible should be preserved, and at least 75% should remain. after completing an initial layout, the ground layer should be checked carefully to make sure there are no isolated ground "islands," because ic ground pins located in a ground "island" have no current return path to the ground plane. also, the ground plane should be checked for "skinny" connections between adjacent large areas which may significantly reduce the effectiveness of the ground plane. needless to say, auto-routing board layout techniques will generally lead to a layout disaster on a mixed-signal board, so manual intervention is highly recommended. systems that are densely packed with surface mount ics will have a large number of interconnections; therefore multilayer boards are mandatory. this allows at least one complete layer to be dedicated to ground. a simple 4-layer board would have internal ground and power plane layers with the outer two layers used for interconnections 9.32

hardware design techniques 9.2 pc board design issues between the surface mount components. placing the power and ground planes adjacent to each other provides additional inter-plane capacitance which helps high frequency decoupling of the power supply. in most systems, 4-layers are not enough, and additional layers are required for routing signals as well as power. figure 9.23 summarizes the key issues relating to ground planes. (cid:139) use large area ground (and power) planes for low impedance current return paths (must use at least a double-sided board!) (cid:139) double-sided boards: (cid:122) avoid high-density interconnection crossovers and vias which reduce ground plane area (cid:122) keep > 75% board area on one side for ground plane (cid:139) multilayer boards: mandatory for dense systems (cid:122) dedicate at least one layer for the ground plane (cid:122) dedicate at least one layer for the power plane (cid:139) use at least 30% to 40% of pcb connector pins for ground (cid:139) continue the ground plane on the backplane motherboard to power supply return figure 9.23: ground planes are mandatory! multicard mixed-signal systems the best way of minimizing ground impedance in a multicard system is to use a "motherboard" pcb as a backplane for interconnections between cards, thus providing a continuous ground plane to the backplane. the pcb connector should have at least 30- 40% of its pins devoted to ground, and these pins should be connected to the ground plane on the backplane mother card. to complete the overall system grounding scheme there are two possibilities: 1. the backplane ground plane can be connected to chassis ground at numerous points, thereby diffusing the various ground current return paths. this is commonly referred to as a "multipoint" grounding system and is shown in figure 9.24. 2. the ground plane can be connected to a single system "star ground" point (generally at the power supply). the first approach is most often used in all-digital systems, but can be used in mixed- signal systems provided the ground currents due to digital circuits are sufficiently low and diffused over a large area. the low ground impedance is maintained all the way through the pc boards, the backplane, and ultimately the chassis. however, it is critical that good electrical contact be made where the grounds are connected to the sheet metal chassis. this requires self-tapping sheet metal screws or "biting" washers. special care must be taken where anodized aluminum is used for the chassis material, since its surface acts as an insulator. 9.33

analog-digital conversion va pcb vd va pcb vd ground plane ground plane ground plane backplane chassis ground power supplies va vd figure 9.24: multipoint ground concept the second approach ("star ground") is often used in high speed mixed-signal systems having separate analog and digital ground systems and warrants further discussion. separating analog and digital grounds in mixed-signal systems with large amounts of digital circuitry, it is highly desirable to physically separate sensitive analog components from noisy digital components. it may also be beneficial to use separate ground planes for the analog and the digital circuitry. these planes should not overlap in order to minimize capacitive coupling between the two. the separate analog and digital ground planes are continued on the backplane using either motherboard ground planes or "ground screens" which are made up of a series of wired interconnections between the connector ground pins. the arrangement shown in figure 9.25 illustrates that the two planes are kept separate all the way back to a common system "star" ground, generally located at the power supplies. the connections between the ground planes, the power supplies, and the "star" should be made up of multiple bus bars or wide copper braids for minimum resistance and inductance. the back-to-back schottky diodes on each pcb are inserted to prevent accidental dc voltage from developing between the two ground systems when cards are plugged and unplugged. this voltage should be kept less than 300 mv to prevent damage to ics which have connections to both the analog and digital ground planes. schottky diodes are preferable because of their low capacitance and low forward voltage drop. the low capacitance prevents ac coupling between the analog and digital ground planes. schottky diodes begin to conduct at about 300 mv, and several parallel diodes in parallel may be required if high currents are expected. in some cases, ferrite beads can be used instead of schottky diodes, however they introduce dc ground loops which can be troublesome in precision systems. 9.34

hardware design techniques 9.2 pc board design issues va pcb vd va pcb vd analog ground plane digital ground plane analog ground plane digital ground plane a d a d digital ground plane analog ground plane system star ground backplane power supplies va vd figure 9.25: separating analog and digital ground planes it is mandatory that the impedance of the ground planes be kept as low as possible, all the way back to the system star ground. dc or ac voltages of more than 300 mv between the two ground planes can not only damage ics but cause false triggering of logic gates and possible latchup. grounding and decoupling mixed-signal ics with low digital currents sensitive analog components such as amplifiers and voltage references are always referenced and decoupled to the analog ground plane. the adcs and dacs (and other mixed-signal ics) with low digital currents should generally be treated as analog components and also grounded and decoupled to the analog ground plane. at first glance, this may seem somewhat contradictory, since a converter has an analog and digital interface and usually has pins designated as analog ground (agnd) and digital ground (dgnd). the diagram shown in figure 9.26 will help to explain this seeming dilemma. inside an ic that has both analog and digital circuits, such as an adc or a dac, the grounds are usually kept separate to avoid coupling digital signals into the analog circuits. figure 9.26 shows a simple model of a converter. there is nothing the ic designer can do about the wirebond inductance and resistance associated with connecting the bond pads on the chip to the package pins except to realize it's there. the rapidly changing digital currents produce a voltage at point b which will inevitably couple into point a of the analog circuits through the stray capacitance, cstray. in addition, there is approximately 0.2-pf unavoidable stray capacitance between every pin of the ic package! it's the ic designer's job to make the chip work in spite of this. however, in order to prevent further coupling, the agnd and dgnd pins should be joined together 9.35

analog-digital conversion externally to the analog ground plane with minimum lead lengths. any extra impedance in the dgnd connection will cause more digital noise to be developed at point b; it will, in turn, couple more digital noise into the analog circuit through the stray capacitance. note that connecting dgnd to the digital ground plane applies vnoise across the agnd and dgnd pins and invites disaster! a ain/ out va ferrite bead va lp rp cstray vd lp rp analog circuits digital circuits data a rp lp a cstray ia id b rp lp agnd dgnd short connections a a = analog ground plane vd see text r buffer gate or register cin ≈ 10pf d data bus vnoise d = digital ground plane d figure 9.26: proper grounding of mixed-signal ics with low internal digital currents the name "dgnd" on an ic tells us that this pin connects to the digital ground of the ic. this does not imply that this pin must be connected to the digital ground of the system. it is true that this arrangement may inject a small amount of digital noise onto the analog ground plane. these currents should be quite small, and can be minimized by ensuring that the converter output does not drive a large fanout (they normally can't, by design). minimizing the fanout on the converter's digital port will also keep the converter logic transitions relatively free from ringing and minimize digital switching currents, and thereby reducing any potential coupling into the analog port of the converter. the logic supply pin (vd) can be further isolated from the analog supply by the insertion of a small lossy ferrite bead as shown in figure 9.26. the internal transient digital currents of the converter will flow in the small loop from vd through the decoupling capacitor and to dgnd (this path is shown with a heavy line on the diagram). the transient digital currents will therefore not appear on the external analog ground plane, but are confined to the loop. the vd pin decoupling capacitor should be mounted as close to the converter as possible to minimize parasitic inductance. these decoupling capacitors should be low inductance ceramic types, typically between 0.01 µf and 0.1 µf. 9.36

hardware design techniques 9.2 pc board design issues treat the adc digital outputs with care it is always a good idea (as shown in figure 9.26) to place a buffer register adjacent to the converter to isolate the converter's digital lines from noise on the data bus. the register also serves to minimize loading on the digital outputs of the converter and acts as a faraday shield between the digital outputs and the data bus. even though many converters have three-state outputs/inputs, this isolation register still represents good design practice. in some cases it may be desirable to add an additional buffer register on the analog ground plane next to the converter output to provide greater isolation. the series resistors (labeled "r" in figure 9.26) between the adc output and the buffer register input help to minimize the digital transient currents which may affect converter performance. the resistors isolate the digital output drivers from the capacitance of the buffer register inputs. in addition, the rc network formed by the series resistor and the buffer register input capacitance acts as a lowpass filter to slow down the fast edges. a typical cmos gate combined with pcb trace and a through-hole will create a load of approximately 10 pf. a logic output slew rate of 1 v/ns will produce 10 ma of dynamic current if there is no isolation resistor: =∆ ci ∆ v ∆ t = 10 pf × v1 ns = 10 ma . eq. 9.2 a 500ω series resistors will minimize this output current and result in a rise and fall time of approximately 11ns when driving the 10pf input capacitance of the register: = 2.2 =τ× 2.2cr2.2 =⋅× × 500 ×ω 10 pf = 11 .ns eq. 9.3 t r ttl registers should be avoided, since they can appreciably add to the dynamic switching currents because of their higher input capacitance. the buffer register and other digital circuits should be grounded and decoupled to the digital ground plane of the pc board. notice that any noise between the analog and digital ground plane reduces the noise margin at the converter digital interface. since digital noise immunity is of the orders of hundreds or thousands of millivolts, this is unlikely to matter. the analog ground plane will generally not be very noisy, but if the noise on the digital ground plane (relative to the analog ground plane) exceeds a few hundred millivolts, then steps should be taken to reduce the digital ground plane impedance, thereby maintaining the digital noise margins at an acceptable level. under no circumstances should the voltage between the two ground planes exceed 300 mv, or the ics may be damaged. separate power supplies for analog and digital circuits are also highly desirable, even if the voltages are the same. the analog supply should be used to power the converter. if the converter has a pin designated as a digital supply pin (vd), it should either be powered from a separate analog supply, or filtered as shown in the diagram. all converter power pins should be decoupled to the analog ground plane, and all logic circuit power pins should be decoupled to the digital ground plane as shown in figure 9.27. 9.37

hardware design techniques 9.2 pc board design issues the effect of sampling clock jitter on adc signal-to-soise ratio (snr) is given approximately by the equation: snr = 20 log 10     1 π ft2     j , eq. 9.4 where snr is the snr of a perfect adc of infinite resolution where the only source of noise is that caused by the rms sampling clock jitter, tj. note that f in the above equation is the analog input frequency. just working through a simple example, if tj = 50 ps rms, f = 100 khz, then snr = 90 db, equivalent to about 15-bit dynamic range. it should be noted that tj in the above example is the root-sum-square (rss) value of the external clock jitter and the internal adc clock jitter (called aperture jitter). however, in most high performance adcs, the internal aperture jitter is negligible compared to the jitter on the sampling clock. since degradation in snr is primarily due to external clock jitter, steps must be taken to ensure the sampling clock is as noise-free as possible and has the lowest possible phase jitter. this requires that a crystal oscillator be used. there are several manufacturers of small crystal oscillators with low jitter (less than 5-ps rms) cmos compatible outputs. (for example, mf electronics, 10 commerce dr., new rochelle, ny 10801, tel. 914- 576-6570 and wenzel associates, inc., 2215 kramer lane, austin, texas 78758 tel. 512- 835-2038). ideally, the sampling clock crystal oscillator should be referenced to the analog ground plane in a split-ground system. however, this is not always possible because of system constraints. in many cases, the sampling clock must be derived from a higher frequency multi-purpose system clock which is generated on the digital ground plane. it must then pass from its origin on the digital ground plane to the adc on the analog ground plane. ground noise between the two planes adds directly to the clock signal and will produce excess jitter. the jitter can cause degradation in the signal-to-noise ratio and also produce unwanted harmonics. this can be remedied somewhat by transmitting the sampling clock signal as a differential signal using either a small rf transformer as shown in figure 9.28 or a high speed differential driver and receiver ic. if an active differential driver and receiver are used, they should be ecl to minimize phase jitter. in a single +5-v supply system, ecl logic can be connected between ground and +5 v (pecl), and the outputs ac coupled into the adc sampling clock input. in either case, the original master system clock must be generated from a low phase noise crystal oscillator, and not the clock output of a dsp, microprocessor, or microcontroller. 9.39

analog-digital conversion digital ground plane analog ground plane vd vd low phase noise master clock system clock generators d vd d dsp or microprocessor sampling clock method 1 d vd a va + _ sampling clock method 2 d d a snr = 20 log10 snr = 20 log10 1 1 2π f tj 2π f tj tj = sampling clock jitter f = analog input frequency figure 9.28: sampling clock distribution from digital to analog ground planes the origins of the confusion about mixed-signal grounding: applying single- card grounding concepts to multicard systems most adc, dac, and other mixed-signal device data sheets discuss grounding relative to a single pcb, usually the manufacturer's own evaluation board. this has been a source of confusion when trying to apply these principles to multicard or multi-adc/dac systems. the recommendation is usually to split the pcb ground plane into an analog plane and a digital plane. it is then further recommended that the agnd and dgnd pins of a converter be tied together and that the analog ground plane and digital ground planes be connected at that same point as shown in figure 9.29. this essentially creates the system "star" ground at the mixed-signal device. all noisy digital currents flow through the digital power supply to the digital ground plane and back to the digital supply; they are isolated from the sensitive analog portion of the board. the system star ground occurs where the analog and digital ground planes are joined together at the mixed signal device. while this approach will generally work in a simple system with a single pcb and single adc/dac, it is not optimum for multicard mixed-signal systems. in systems having several adcs or dacs on different pcbs (or on the same pcb, for that matter), the analog and digital ground planes become connected at several points, creating the possibility of ground loops and making a single- point "star" ground system impossible. for these reasons, this grounding approach is not recommended for multicard systems, and the approach previously discussed should be used for mixed signal ics with low digital currents. 9.40

hardware design techniques 9.2 pc board design issues system star ground va vd analog circuits vd va mixed signal device agnd dgnd digital circuits a a d d analog ground plane digital ground plane a d analog supply digital supply figure 9.29: grounding mixed signal ics : single pc board (typical evaluation/test board) summary: grounding mixed signal devices with low digital currents in a multicard system figure 9.30 summarizes the approach previously described for grounding a mixed signal device which has low digital currents. the analog ground plane is not corrupted because the small digital transient currents flow in the small loop between vd, the decoupling capacitor, and dgnd (shown as a heavy line). the mixed signal device is for all intents and purposes treated as an analog component. the noise vn between the ground planes reduces the noise margin at the digital interface but is generally not harmful if kept less than 300 mv by using a low impedance digital ground plane all the way back to the system star ground. however, mixed signal devices such as sigma-delta adcs, codecs, and dsps with on- chip analog functions are becoming more and more digitally intensive. along with the additional digital circuitry come larger digital currents and noise. for example, a sigma- delta adc or dac contains a complex digital filter which adds considerably to the digital current in the device. the method previously discussed depends on the decoupling capacitor between vd and dgnd to keep the digital transient currents isolated in a small loop. however, if the digital currents are significant enough and have components at dc or low frequencies, the decoupling capacitor may have to be so large that it is impractical. any digital current which flows outside the loop between vd and dgnd must flow through the analog ground plane. this may degrade performance, especially in high resolution systems. 9.41

analog-digital conversion vn vn = noise between ground planes va filter vd analog circuits vd r va mixed signal device agnd dgnd bus buffer latch digital circuits a a a d d analog ground plane digital ground plane a a d d to system analog supply to system digital supply to system star ground figure 9.30: grounding mixed signal ics with low internal digital currents: multiple pc boards it is difficult to predict what level of digital current flowing into the analog ground plane will become unacceptable in a system. all we can do at this point is to suggest an alternative grounding method which may yield better performance. summary: grounding mixed signal devices with high digital currents in a multicard system an alternative grounding method for a mixed signal device with high levels of digital currents is shown in figure 9.31. the agnd of the mixed signal device is connected to the analog ground plane, and the dgnd of the device is connected to the digital ground plane. the digital currents are isolated from the analog ground plane, but the noise between the two ground planes is applied directly between the agnd and dgnd pins of the device. for this method to be successful, the analog and digital circuits within the mixed signal device must be well isolated. the noise between agnd and dgnd pins must not be large enough to reduce internal noise margins or cause corruption of the internal analog circuits. figure 9.31 shows optional schottky diodes (back-to-back) or a ferrite bead connecting the analog and digital ground planes. the schottky diodes prevent large dc voltages or low frequency voltage spikes from developing across the two planes. these voltages can potentially damage the mixed signal ic if they exceed 300 mv because they appear directly between the agnd and dgnd pins. as an alternative to the back-to-back schottky diodes, a ferrite bead provides a dc connection between the two planes but isolates them at frequencies above a few mhz where the ferrite bead becomes resistive. this protects the ic from dc voltages between agnd and dgnd, but the dc connection 9.42

hardware design techniques 9.2 pc board design issues provided by the ferrite bead can introduce unwanted dc ground loops and may not be suitable for high resolution systems. vn vn = noise between ground planes va vd (cid:146) back-to-back schottky diodes or ferrite bead (see text) analog circuits va vd mixed signal device agnd dgnd digital circuits a a d d (cid:146) analog ground plane digital ground plane a a d d to system analog supply to system star ground to system digital supply figure 9.31: grounding alternative for mixed-signal ics with high digital currents: multiple pc boards grounding dsps with internal phase-locked loops as if dealing with mixed-signal ics with agnd and dgnds wasn't enough, dsps such as the adsp-21160 sharc with internal phase-locked-loops (plls) raise issues with respect to proper grounding. the adsp-21160 pll allows the internal core clock (determines the instruction cycle time) to operate at a user-selectable ratio of 2, 3, or 4 times the external clock frequency, clkin. the clkin rate is the rate at which the synchronous external ports operate. although this allows using a lower frequency external clock, care must be taken with the power and ground connections to the internal pll as shown in figure 9.32. in order to prevent internal coupling between digital currents and the pll, the power and ground connections to the pll are brought out separately on pins labeled avdd and agnd, respectively. the avdd +2.5-v supply should be derived from the vdd int +2.5-v supply using the filter network as shown. this ensures a relatively noise-free supply for the internal pll. the agnd pin of the pll should be connected to the digital ground plane of the pc board using a short trace. the decoupling capacitors should be routed between the avdd pin and agnd pin using short traces. 9.43

hardware design techniques 9.2 pc board design issues (cid:139) there is no single grounding method which is guaranteed to work 100% of the time! (cid:139) different methods may or may not give the same levels of performance. (cid:139) at least one layer on each pc board must be dedicated to ground plane! (cid:139) do initial layout with split analog and digital ground planes. (cid:139) provide pads and vias on each pc board for back-to-back schottky diodes and optional ferrite beads to connect the two planes. (cid:139) provide "jumpers" so that dgnd pins of mixed-signal devices can be connected to agnd pins (analog ground plane) or to digital ground plane. (agnd of plls in dsps should be connected to digital ground plane). (cid:139) provide pads and vias for "jumpers" so that analog and digital ground planes can be joined together at several points on each pc board. (cid:139) follow recommendations on mixed signal device data sheet. figure 9.33: grounding philosophy summary some general pc board layout guidelines for mixed-signal systems it is evident that noise can be minimized by paying attention to the system layout and preventing different signals from interfering with each other. high level analog signals should be separated from low level analog signals, and both should be kept away from digital signals. we have seen elsewhere that in waveform sampling and reconstruction systems the sampling clock (which is a digital signal) is as vulnerable to noise as any analog signal, but is as liable to cause noise as any digital signal, and so must be kept isolated from both analog and digital systems. if clock driver packages are used in clock distribution, only one frequency clock should be passed through a single package. sharing drivers between clocks of different frequencies in the same package will produce excess jitter and crosstalk and degrade performance. the ground plane can act as a shield where sensitive signals cross. figure 9.34 shows a good layout for a data acquisition board where all sensitive areas are isolated from each other and signal paths are kept as short as possible. while real life is rarely as tidy as this, the principle remains a valid one. there are a number of important points to be considered when making signal and power connections. first of all a connector is one of the few places in the system where all signal conductors must run in parallel—it is therefore imperative to separate them with ground pins (creating a faraday shield) to reduce coupling between them. multiple ground pins are important for another reason: they keep down the ground impedance at the junction between the board and the backplane. the contact resistance of a single pin of a pcb connector is quite low (of the order of 10 mω) when the board is new—as the board gets older the contact resistance is likely to rise, and the board's performance may be compromised. it is therefore well worthwhile to allocate extra pcb connector pins so that there are many ground connections (perhaps 30-40% of all the pins 9.45

analog-digital conversion on the pcb connector should be ground pins). for similar reasons there should be several pins for each power connection, although there is no need to have as many as there are ground pins. sampling clock generator timing circuits control logic reference adc buffer register demultiplexer analog filter digital amplifier dsp or µp buffer memory power multiple grounds analog input data bus address bus multiple grounds figure 9.34: analog and digital circuits should be partitioned on pcb layout analog devices and other manufacturers of high performance mixed-signal ics offer evaluation boards to assist customers in their initial evaluations and layout. adc evaluation boards generally contain an on-board low-jitter sampling clock oscillator, output registers, and appropriate power and signal connectors. they also may have additional support circuitry such as the adc input buffer amplifier and external reference. the layout of the evaluation board is optimized in terms of grounding, decoupling, and signal routing and can be used as a model when laying out the adc pc board in the system. the actual evaluation board layout is usually available from the adc manufacturer in the form of computer cad files (gerber files). in many cases, the layout of the various layers appears on the data sheet for the device. skin effect at high frequencies, also consider skin effect, where inductive effects cause currents to flow only in the outer surface of conductors. note that this is in contrast to the earlier discussions of this section on dc resistance of conductors. the skin effect has the consequence of increasing the resistance of a conductor at high frequencies. note also that this effect is separate from the increase in impedance due to the effects of the self-inductance of conductors as frequency is increased. 9.46

analog-digital conversion figure 9.36 illustrates a case of a pcb conductor with current flow, as separated from the ground plane underneath. in this diagram, note the (dotted) regions of high frequency current flow, as reduced by the skin effect. when calculating skin effect in pcbs, it is important to remember that current generally flows in both sides of the pc foil (this is not necessarily the case in microstrip lines, see below), so the resistance per square of pc foil may be half the above value. transmission lines we earlier considered the benefits of outward and return signal paths being close together so that inductance is minimized. as shown previously in figure 9.36, when a high frequency signal flows in a pc track running over a ground plane, the arrangement functions as a microstrip transmission line, and the majority of the return current flows in the ground plane underneath the line. figure 9.37 shows the general parameters for a microstrip transmission line, given the conductor width, w, dielectric thickness, h, and the dielectric constant, er. the characteristic impedance of such a microstrip line will depend upon the width of the track and the thickness and dielectric constant of the pcb material. designs of microstrip lines are covered in more detail later in this chapter. conductor conductor dielectric dielectric w w h h ground plane ground plane figure 9.37: a pcb microstrip transmission line is an example of a controlled impedance conductor pair for most dc and lower frequency applications, the characteristic impedance of pcb traces will be relatively unimportant. even at frequencies where a track over a ground plane behaves as a transmission line, it is not necessary to worry about its characteristic impedance or proper termination if the free space wavelengths of the frequencies of interest are greater than ten times the length of the line. however, at vhf and higher frequencies it is possible to use pcb tracks as microstrip lines within properly terminated transmission systems. typically the microstrip will be designed to match standard coaxial cable impedances, such as 50, 75 or 100 ω, simplifying interfacing. 9.48

hardware design techniques 9.2 pc board design issues note that if losses in such systems are to be minimized, the pcb material must be chosen for low high-frequency losses. this usually means the use of teflon or some other comparably low-loss pcb material. often, though, the losses in short lines on cheap glass-fiber board are small enough to be quite acceptable. be careful with ground plane breaks wherever there is a break in the ground plane beneath a conductor, the ground plane return current must by necessity flow around the break. as a result, both the inductance and the vulnerability of the circuit to external fields are increased. this situation is diagrammed in figure 9.38, where conductors a and b must cross one another. where such a break is made to allow a crossover of two perpendicular conductors, it would be far better if the second signal were carried across both the first and the ground plane by means of a piece of wire or a resistor. the ground plane then acts as a shield between the two signal conductors, and the two ground return currents, flowing in opposite sides of the ground plane as a result of skin effects, do not interact. with a multi-layer board, both the crossover and the continuous ground plane can be accommodated without the need for a wire link. multi-layer pcbs are expensive and harder to trouble-shoot than more simple double-sided boards, but do offer even better shielding and signal routing. the principles involved remain unchanged but the range of layout options is increased. signal current b (cid:139) this view from pcb conductor (track) side (cid:139) note: return currents a & b may interact return current b diverts around ground plane break, raising inductance break in ground plane crossover “b” on ground plane side signal current a return current a diverts around ground plane break, raising inductance figure 9.38: a ground plane break raises circuit inductance, and increases vulnerability to external fields 9.49

analog-digital conversion the use of double-sided or multi-layer pcbs with at least one continuous ground plane is undoubtedly one of the most successful design approaches for high performance mixed signal circuitry. often the impedance of such a ground plane is sufficiently low to permit the use of a single ground plane for both analog and digital parts of the system. however, whether or not this is possible does depend upon the resolution and bandwidth required, and the amount of digital noise present in the system. ground isolation techniques while the use of ground planes does lower impedance and helps greatly in lowering ground noise, there may still be situations where a prohibitive level of noise exists. in such cases, the use of ground error minimization and isolation techniques can be helpful. another illustration of a common-ground impedance coupling problem is shown in figure 9.39. in this circuit a precision gain-of-100 preamp amplifies a low-level signal vin, using an ad8551 chopper-stabilized amplifier for best dc accuracy. at the load end, the signal vout is measured with respect to g2, the local ground. because of the small 700-µa isupply of the ad8551 flowing between g1 and g2, there is a 7-µv ground error—about 7 times the typical input offset expected from the op amp! vin 5mv fs isupply 700µa +5v u1 ad8551 r1 99kω r2 1kω g1 rground 0.01ω ∆v ≅ 7µv vout g2 figure 9.39: unless care is taken, even small common ground currents can degrade precision amplifier accuracy this error can be avoided by routing the negative supply pin current of the op amp back to star ground g2 as opposed to ground g1, by using a separate trace. this step eliminates the g1-g2 path power supply current, and so minimizes the ground leg voltage error. note that there will be little error developed in the "hot" vout lead, so long as the current drain at the load end is small. in some cases, there may be simply unavoidable ground voltage differences between a source signal and the load point where it is to be measured. within the context of this "same-board" discussion, this might require rejecting ground error voltages of several tens-of-mv. or, should the source signal originate from an "off-board" source, then the magnitude of the common-mode voltages to be rejected can easily rise into a several volt range (or even tens-of-volts). 9.50

hardware design techniques 9.2 pc board design issues fortunately, full signal transmission accuracy can still be accomplished in the face of such high noise voltages, by employing a principle discussed earlier. this is the use of a differential-input, ground isolation amplifier. the ground isolation amplifier minimizes the effect of ground error voltages between stages by processing the signal in differential fashion, thereby rejecting common-mode voltages by a substantial margin (typically 60 db or more). note that this approach is only effective for very low frequency signals, however. two ground isolation amplifier solutions are shown in figure 9.40. this diagram can alternately employ either the ad629 to handle cm voltages up to ±270 v, or the amp03, which is suitable for cm voltages up to ±20 v. r5 21.1kω (ad629 only) r1 380kω / 25kω r2 380kω / 25kω g2 vin ad629 / amp03 difference amplifiers r3 380kω / 25kω r4 20kω / 25kω g1 input common ∆v ground noise cmv(v) cmr(db) ad629 ± 270 amp03 ± 20 88 100 vout g2 output common figure 9.40: a differential input ground isolating amplifier allows high transmission accuracy by rejecting ground noise voltage between source (g1) and measurement (g2) grounds in the circuit, input voltage vin is referred to g1, but must be measured with respect to g2. with the use of a high cmr unity-gain difference amplifier, the noise voltage ∆v existing between these two grounds is easily rejected. the ad629 offers a typical cmr of 88 db, while the amp03 typically achieves 100 db. in the ad629, the high cmv rating is done by a combination of high cm attenuation, followed by differential gain, realizing a net differential gain of unity. the ad629 uses the first listed value resistors noted in the figure for r1-r5. the amp03 operates as a precision four-resistor differential amplifier, using the 25-kω value r1-r4 resistors noted. both devices are complete, one package solutions to the ground-isolation amplifier. this scheme allows relative freedom from tightly controlling ground drop voltages, or running additional and/or larger pcb traces to minimize such error voltages. note that it can be implemented either with the fixed gain difference amplifiers shown, or also with a 9.51

analog-digital conversion standard in-amp ic, configured for unity gain. the ad623, for example, also allows single-supply use. in any case, signal polarity is also controllable, by simple reversal of the difference amplifier inputs. in general terms, transmitting a signal from one point on a pcb to another for measurement or further processing can be optimized by two key interrelated techniques. these are the use of high-impedance, differential signal-handling techniques. the high impedance loading of an in-amp minimizes voltage drops, and differential sensing of the remote voltage minimizes sensitivity to ground noise. when the further signal processing is a/d conversion, these transmission criteria can be implemented without adding a differential ground isolation amplifier stage. simply select an adc which operates differentially. the high input impedance of the adc minimizes load sensitivity to the pcb wiring resistance. in addition, the differential input feature allows the output of the source to be sensed directly at the source output terminals (even if single-ended). the cmr of the adc then eliminates sensitivity to noise voltages between the adc and source grounds. an illustration of this concept using an adc with high impedance differential inputs is shown in figure 9.41. note that the general concept can be extended to virtually any signal source, driving any load. all loads, even single-ended ones, become differential- input by adding an appropriate differential input stage. signal source vout high-z differential input adc ground path errors not critical figure 9.41: a high-impedance differential input adc also allows high transmission accuracy between source and load the differential input can be provided by either a fully developed high-z in-amp, or in many cases it can be a simple subtractor stage op amp, such as figure 9.40. static pcb effects leakage resistance is the dominant static circuit board effect. contamination of the pcb surface by flux residues, deposited salts, and other debris can create leakage paths between circuit nodes. even on well-cleaned boards, it is not unusual to find 10 na or more of leakage to nearby nodes from 15-v supply rails. nanoamperes of leakage current into the wrong nodes often cause volts of error at a circuit's output; for example, 10 na into a 10-mω resistance causes a 0.1-v error. unfortunately, the standard op amp pinout 9.52

hardware design techniques 9.2 pc board design issues places the –vs supply pin next to the + input, which is often hoped to be at high impedance! to help identify nodes sensitive to the effects of leakage currents ask the simple question: if a spurious current of a few nanoamperes or more were injected into this node, would it matter? if the circuit is already built, you can localize moisture sensitivity to a suspect node with a classic test. while observing circuit operation, blow on potential trouble spots through a simple soda straw. the straw focuses the breath's moisture, which, with the board's salt content in susceptible portions of the design, disrupts circuit operation upon contact. there are several means of eliminating simple surface leakage problems. thorough washing of circuit boards to remove residues helps considerably. a simple procedure includes vigorously brushing the boards with isopropyl alcohol, followed by thorough washing with deionized water and an 85°c bakeout for a few hours. be careful when selecting board-washing solvents, though. when cleaned with certain solvents, some water-soluble fluxes create salt deposits, exacerbating the leakage problem. unfortunately, if a circuit displays sensitivity to leakage, even the most rigorous cleaning can offer only a temporary solution. problems soon return upon handling, or exposure to foul atmospheres, and high humidity. some additional means must be sought to stabilize circuit behavior, such as conformal surface coating. fortunately, there is an answer to this, namely guarding, which offers a fairly reliable and permanent solution to the problem of surface leakage. well-designed guards can eliminate leakage problems, even for circuits exposed to harsh industrial environments. two schematics illustrate the basic guarding principle, as applied to typical inverting and non-inverting op amp circuits. figure 9.42 illustrates an inverting mode guard application. in this case, the op amp reference input is grounded, so the guard is a grounded ring surrounding all leads to the inverting input, as noted by the dotted line. inverting mode guard: ring surrounds all lead ends at the "hot node" and nothing else figure 9.42: inverting mode guard encloses all op amp inverting input connections within a grounded guard ring 9.53

analog-digital conversion basic guarding principles are simple: completely surround sensitive nodes with conductors that can readily sink stray currents, and maintain the guard conductors at the exact potential of the sensitive node (as otherwise the guard will serve as a leakage source rather than a leakage sink). for example, to keep leakage into a node below 1 pa (assuming 1000-mω leakage resistance) the guard and guarded node must be within 1 mv. generally, the low offset of a modern op amp is sufficient to meet this criterion. there are important caveats to be noted with implementing a true high-quality guard. for traditional through-hole pcb connections, the guard pattern should appear on both sides of the circuit board, to be most effective. and, it should also be connected along its length by several vias. finally, when either justified or required by the system design parameters, do make an effort to include guards in the pcb design process from the outset—there is little likelihood that a proper guard can be added as an afterthought. figure 9.43 illustrates the case for a non-inverting guard. in this instance the op amp reference input is directly driven by the source, which complicates matters considerably. again, the guard ring completely surrounds all of the input nodal connections. in this instance however, the guard is driven from the low impedance feedback divider connected to the inverting input. usually the guard-to-divider junction will be a direct connection, but in some cases a unity gain buffer might be used at "x" to drive a cable shield, or also to maintain the lowest possible impedance at the guard ring. y non-inverting mode guard: ring surrounds all "ho t node" l ead e nds - including input terminal on the pcb y r l x y y lo w value gain resistors use shielding (y) or unity-gain buffer (x) if guard has long lead figure 9.43: non-inverting mode guard encloses all op amp non-inverting input connections within a low impedance, driven guard ring in lieu of the buffer, another useful step is to use an additional, directly grounded screen ring, "y", which surrounds the inner guard and the feedback nodes as shown. this step 9.54

hardware design techniques 9.2 pc board design issues costs nothing except some added layout time, and will greatly help buffer leakage effects into the higher impedance inner guard ring. of course what hasn’t been addressed to this point is just how the op amp itself gets connected into these guarded islands without compromising performance. the traditional method using a to-99 metal can package device was to employ double-sided pcb guard rings, with both op amp inputs terminated within the guarded ring. many high impedance sensors use the above-described method. the section immediately following illustrates how more modern ic packages can be mounted to pcb patterns, and take advantage of guarding and low-leakage operation. sample minidip and soic op amp pcb guard layouts modern assembly practices have favored smaller plastic packages such as 8-pin minidip and soic types. some suggested partial layouts for guard circuits using these packages is shown in the next two figures. while guard traces may also be possible with even more tiny op amp footprints, such as sot23, sc70, etc., the required trace separations become even more confining, challenging the layout designer as well as the manufacturing processes. for the adi "n" style minidip package, figure 9.44 illustrates how guarding can be accomplished for inverting (left) and non-inverting (right) operating modes. this setup would also be applicable to other op amp devices where relatively high voltages occur at pin 1 or 4. using a standard 8-pin dip outline for a single op amp, it can be noted that this package's 0.1" pin spacing allows a pc trace (here, the guard trace) to pass between adjacent pins. this is the key to implementing effective dip package guarding, as it can adequately prevent a leakage path from the –vs supply at pin 4, or from similar high potentials at pin 1. guard guard input input guard guard 1 1 2 2 3 3 4 4 8 8 7 7 6 6 5 5 guard guard input input guard guard 1 1 2 2 3 3 4 4 8 8 7 7 6 6 5 5 inverting mode inverting mode guard pattern guard pattern non-inverting mode non-inverting mode guard pattern guard pattern figure 9.44: pcb guard patterns for inverting and non-inverting mode op amps using 8 pin minidip (n) package for the left-side inverting mode, note that the grounded guard traces connected to pin 3 surround the op amp inverting input (pin 2), and run parallel to the input trace. this guard would be continued out to and around the source and feedback connections of figure 9.42 (or other similar circuit), including an input pad in the case of a cable. in the 9.55

analog-digital conversion right-side non-inverting mode, the guard voltage is the feedback divider voltage to pin 2. this corresponds to the inverting input node of the amplifier, from figure 9.43. note that in both of the cases of figure 9.44, the guard physical connections shown are only partial—an actual layout would include all sensitive nodes within the circuit. in both the inverting and the non-inverting modes using the minidip or other through-hole style package, the pcb guard traces should be located on both sides of the board, with top and bottom traces connected with several vias. things become slightly more complicated when using guarding techniques with the soic surface mount ("r") package, as the 0.05" pin spacing doesn't easily allow routing of pcb traces between the pins. but, there is still an effective guarding answer, at least for the inverting case. figure 9.45 shows guards for the adi "r" style soic package. note that for many single op amp devices in this soic "r" package, pins 1, 5, and 8 are "no connect" pins. for such instances, this means that these locations can be employed in the layout to route guard traces. in the case of the inverting mode (left), the guarding is still completely effective, with the dummy pin 1 and pin 3 serving as the grounded guard trace. this is a fully effective guard without compromise. also, with soic op amps, much of the circuitry around the device will not use through-hole components. so, the guard ring may only be necessary on the op amp pcb side. note: pins 1, 5, & 8 are open on many “r” packaged devices guard input guard 1 2 3 4 –vs 8 7 6 5 guard input guard 1 2 3 4 –vs 8 7 6 5 inverting mode guard pattern non-inverting mode guard pattern figure 9.45: pcb guard patterns for inverting and non-inverting mode op amps using 8 pin soic (r) package in the case of the follower stage (right), the guard trace must be routed around the negative supply at pin 4, and thus pin 4 to pin 3 leakage isn't fully guarded. for this reason, a precision high impedance follower stage using an soic package op amp isn’t generally recommended, as guarding isn't as effective for dual supply connected devices. however, an exception to this caveat does apply to the use of a single-supply op amp as a non-inverting stage. for example, if the ad8551 is used, pin 4 becomes ground, and some degree of intrinsic guarding is then established by default. 9.56

hardware design techniques 9.2 pc board design issues dynamic pcb effects although static pcb effects can come and go with changes in humidity or board contamination, problems that most noticeably affect the dynamic performance of a circuit usually remain relatively constant. short of a new design, washing or any other simple fixes can't fix them. as such, they can permanently and adversely affect a design's specifications and performance. the problems of stray capacitance, linked to lead and component placement, are reasonably well known to most circuit designers. since lead placement can be permanently dealt with by correct layout, any remaining difficulty is solved by training assembly personnel to orient components or bend leads optimally. dielectric absorption (da), on the other hand, represents a more troublesome and still poorly understood circuit-board phenomenon. like da in discrete capacitors, da in a printed-circuit board can be modeled by a series resistor and capacitor connecting two closely spaced nodes. its effect is inverse with spacing and linear with length. as shown in figure 9.46, the rc model for this effective capacitance ranges from 0.1 to 2.0 pf, with the resistance ranging from 50 to 500 mω. values of 0.5 pf and 100 mω are most common. consequently, circuit-board da interacts most strongly with high-impedance circuits. 0.05" (1.3mm) 0.05" (1.3mm) 50 - 500mω 50 - 500mω 0.1- 2.0 pf 0.1- 2.0 pf cstray cstray rleakage rleakage figure 9.46: da plagues dynamic response of pcb-based circuits pcb da most noticeably influences dynamic circuit response, for example, settling time. unlike circuit leakage, the effects aren't usually linked to humidity or other environmental conditions, but rather, are a function of the board's dielectric properties. the chemistry involved in producing plated-through holes seems to exacerbate the problem. if your circuits don't meet expected transient response specs, you should consider pcb da as a possible cause. fortunately, there are solutions. as in the case of capacitor da, external components can be used to compensate for the effect. more importantly, surface guards that totally isolate sensitive nodes from parasitic coupling often eliminate the problem (note that these guards should be duplicated on both sides of the board, in cases of through-hole components). as noted previously, low-loss pcb dielectrics are also available at higher costs. 9.57

analog-digital conversion pcb "hook", similar if not identical to da, is characterized by variation in effective circuit-board capacitance with frequency (see reference 1). in general, it affects high-impedance circuit transient response where board capacitance is an appreciable portion of the total in the circuit. circuits operating at frequencies below 10 khz are the most susceptible. as in circuit board da, the board's chemical makeup very much influences its effects. stray capacitance when two conductors aren't short-circuited together, or totally screened from each other by a conducting (faraday) screen, there is a capacitance between them. so, on any pcb, there will be a large number of capacitors associated with any circuit (which may or may not be considered in models of the circuit). where high frequency performance matters (and even dc and vlf circuits may use devices with high ft and therefore be vulnerable to high frequency instability), it is very important to consider the effects of this stray capacitance. any basic textbook will provide formulas for the capacitance of parallel wires and other geometric configurations (see references 9 and 10). the example we need consider in this discussion is the parallel plate capacitor, often formed by conductors on opposite sides of a pcb. the basic diagram describing this capacitance is shown in figure 9.47. c = 0.00885 e a r d pf a d a = plate area in mm 2 d = plate separation in mm e = dielectric constant relative to air r (cid:139) most common pcb type uses 1.5mm glass-fiber epoxy material with e = 4.7 r (cid:139) capacity of pc track over ground plane is roughly 2.8pf/cm 2 figure 9.47: capacitance of two parallel plates neglecting edge effects, the capacitance of two parallel plates of area a mm2 and separation d mm in a medium of dielectric constant er relative to air is 0.00885 er a/d pf. from this formula, we can calculate that for general purpose pcb material (er = 4.7, d = 1.5 mm), the capacitance between conductors on opposite sides of the board is just under 3 pf/cm2. in general, such capacitance will be parasitic, and circuits must be designed so that it does not affect their performance. 9.58

hardware design techniques 9.2 pc board design issues while it is possible to use pcb capacitance in place of small discrete capacitors, the dielectric properties of common pcb substrate materials cause such capacitors to behave poorly. they have a rather high temperature coefficient and poor q at high frequencies, which makes them unsuitable for many applications. boards made with lower-loss dielectrics such as teflon are expensive exceptions to this rule. capacitive noise and faraday shields there is a capacitance between any two conductors separated by a dielectric (air or vacuum are dielectrics). if there is a change of voltage on one, there will be a movement of charge on the other. a basic model for this is shown in figure 9.48. c in vn z1 vcoupled z1 = circuit impedance z2 = 1/jωc vcoupled = vn    z1 z1 + z2    figure 9.48: capacitive coupling equivalent circuit model it is evident that the noise voltage, vcoupled appearing across z1, may be reduced by several means, all of which reduce noise current in z1. they are reduction of the signal voltage vn, reduction of the frequency involved, reduction of the capacitance, or reduction of z1 itself. unfortunately however, often none of these circuit parameters can be freely changed, and an alternate method is needed to minimize the interference. the best solution towards reducing the noise coupling effect of c is to insert a grounded conductor, also known as a faraday shield, between the noise source and the affected circuit. this has the desirable effect of reducing z1 noise current, thus reducing vcoupled. a faraday shield model is shown by figure 9.49. in the left picture, the function of the shield is noted by how it effectively divides the coupling capacitance, c. in the right picture the net effect on the coupled voltage across z1 is shown. although the noise current in still flows in the shield, most of it is now diverted away from z1. as a result, the coupled noise voltage vcoupled across z1 is reduced. a faraday shield is easily implemented and almost always successful. thus capacitively coupled noise is rarely an intractable problem. however, to be fully effective, a faraday shield must completely block the electric field between the noise source and the shielded circuit. it must also be connected so that the displacement current returns to its source, without flowing in any part of the circuit where it can introduce conducted noise. 9.59

analog-digital conversion capacitive capacitive shield shield c c in in vn vn z1 z1 vcoupled vcoupled vn vn in in z1 z1 vcoupled vcoupled figure 9.49: an operational model of a faraday shield the floating shield problem and, it is quite important to note here—a conductor that is intended to function as a faraday shield must never be left floating, as this almost always increases capacity and exacerbates the noise problem! an example of this "floating shield" problem is seen in side-brazed ceramic ic packages. these dip packages have a small square conducting kovar lid soldered onto a metallized rim on the ceramic package top. package manufacturers offer only two options: the metallized rim may be connected to one of the corner pins of the package, or it may be left unconnected. most logic circuits have a ground pin at one of the package corners, and therefore the lid is grounded. alas, many analog circuits don't have a ground pin at a package corner, and the lid is left floating—acting as an antenna for noise. such circuits turn out to be far more vulnerable to electric field noise than the same chip in a plastic dip package, where the chip is completely unshielded. whenever practical, it is good practice for the user to ground the lid of any side brazed ceramic ic where the lid is not grounded by the manufacturer, thus implementing an effective faraday shield. this can be done with a wire soldered to the lid (this will not damage the device, as the chip is thermally and electrically isolated from the lid). if soldering to the lid is unacceptable, a grounded phosphor-bronze clip or conductive paint from the lid to the ground pin may be used to make the ground connection,. a safety note is appropriate at this point. never attempt to ground such a lid without first verifying that it is unconnected. occasionally device types are found with the lid connected to a power supply rather than to ground! a case where a faraday shield is impractical is between ic chip bondwires. this can have important consequences, as the stray capacitance between chip bondwires and associated leadframes is typically ≈ 0.2 pf, with observed values generally between 0.05 and 0.6 pf. buffering adcs against logic noise if we have a high resolution data converter (adc or dac) connected to a high speed data bus which carries logic noise with a 2-5 v/ns edge rate, this noise is easily connected 9.60

hardware design techniques 9.2 pc board design issues references: 9.2 pc board design issues 1. w. doeling, w. mark, t. tadewald, and p. reichenbacher, "getting rid of hook: the hidden pc-board capacitance," electronics, october 12, 1978, p 111-117. 2. alan rich, "shielding and guarding", analog dialogue, vol. 17 n0. 1, 1983, pp. 8. 3. ralph morrison, grounding and shielding techniques, 4th edition, john wiley, inc., 1998, isbn: 0471245186. 4. henry w. ott, noise reduction techniques in electronic systems, 2nd edition, john wiley, inc., 1988, isbn: 0-471-85068-3. 5. paul brokaw, "an ic amplifier user's guide to decoupling, grounding and making things go right for a change", analog devices an202. 6. paul brokaw, "analog signal-handling for high speed and accuracy," analog devices an342. 7. paul brokaw and jeff barrow, "grounding for low- and high-frequency circuits," analog devices an345. jeff barrow, "avoiding ground problems in high speed circuits," rf design, july 1989. 8. 9. b. i. & b. bleaney, electricity & magnetism, oxford at the clarendon press, 1957, pp 23, 24, & 52. 10. g. w. a. dummer, h. nordenberg, fixed and variable capacitors, mcgraw-hill, 1960, pp 11-13. 11. william c. rempfer, get all the fast adc bits you pay for, electronic design, special analog issue, june 24, 1996, p.44. 12. mark sauerwald, keeping analog signals pure in a hostile digital world, electronic design, special analog issue, june 24, 1996, p.57. 13. jerald grame and bonnie baker, design equations help optimize supply bypassing for op amps, electronic design, special analog issue, june 24, 1996, p.9. 14. jerald grame and bonnie baker, fast op amps demand more than a single-capacitor bypass, electronic design, special analog issue, november 18, 1996, p.9. 15. walt kester and james bryant, grounding in high speed systems, high speed design techniques, analog devices, 1996, chapter 7, p. 7-27. 16. jeffrey s. pattavina, bypassing pc boards: thumb your nose at rules of thumb, edn, oct. 22, 1998, p.149. 17. howard w. johnson and martin graham, high-speed digital design, ptr prentice hall, 1993, isbn: 0133957241. 18. walt kester, a grounding philosophy for mixed-signal systems, electronic design analog applications issue, june 23, 1997, p. 29. 19. ralph morrison, solving interference problems in electronics, john wiley, 1995. 20. c. d. motchenbacher and j. a. connelly, low noise electronic system design, john wiley, 1993. 21. crystal oscillators: mf electronics, 10 commerce drive, new rochelle, ny, 10801, 914-576-6570. 9.63

hardware design techniques 9.3 analog power supply systems section 9.3: analog power supply systems walt jung, walt kester analog circuits have traditionally been powered from well-regulated, low noise linear power supplies. this type of power system is typically characterized by medium-to-low power conversion efficiency. such linear regulators usually excel in terms of self- generated and radiated noise components. if the designer's life were truly simple, it might continue with such familiar designs offering good performance and minimal side effects. but, the designer's life is hardly so simple. modern systems may allow using linear regulators, but multiple output levels and/or polarities are often required. there may also be some additional requirements set for efficiency, which may dictate the use of dc-dc conversion techniques, and, unfortunately, their higher associated noise output. this section addresses power supply design issues for analog systems (including op amps, analog multiplexers, adcs, dacs, etc.), taking into account the regulator types most likely to be used. the primary dc power sources are assumed to be either rectified and smoothed ac sources (i.e., mains derived), a battery stack, or a switching regulator output. the latter example could be fed from either a battery or a mains-derived dc source. as noted in figure 9.52, linear mode regulation is generally recommended as an optimum starting point in all instances (first bullet). nevertheless, in some cases, a degree of hybridization between fully linear and switching mode regulation may be required (second bullet). this could be either for efficiency or other diverse reasons. (cid:139) high performance analog power systems use linear regulators, with primary power derived from: (cid:122) ac line power (cid:122) battery power systems (cid:122) dc- dc power conversion systems (cid:139) switching regulators should be avoided if at all possible, but if not… (cid:122) apply noise control techniques (cid:122) use quality layout and grounding (cid:122) be aware of emi figure 9.52: regulation priorities for analog power supply systems whenever switching-type regulators are involved in powering precision analog circuits, noise control is very likely to be a design issue. therefore some focus of this section is on minimizing noise when using switching regulators. 9.65

analog-digital conversion linear ic regulation linear ic voltage regulators have long been standard power system building blocks. after an initial introduction in 5-v logic voltage regulator form, they have since expanded into other standard voltage levels spanning from 3 to 24 v, handling output currents from as low as 100 ma (or less) to as high as 5 a (or more). for several good reasons, linear style ic voltage regulators have been valuable system components since the early days. as mentioned above, a basic reason is the relatively low noise characteristic vis-à-vis the switching type of regulator. others are a low parts count and overall simplicity compared to discrete solutions. but, because of their power losses, these linear regulators have also been known for being relatively inefficient. early generation devices (of which many are still available) required 2v or more of unregulated input above the regulated output voltage, making them lossy in power terms. more recently however, linear ic regulators have been developed with more liberal (i.e., lower) limits on minimum input-output voltage. this voltage, known more commonly as dropout voltage, has led to what is termed the low drop out regulator, or more simply, the ldo. dropout voltage (vmin) is defined simply as that minimum input-output differential where the regulator undergoes a 2% reduction in output voltage. for example, if a nominal 5.0-v ldo output drops to 4.9 v (–2%) under conditions of an input-output differential of 0.5 v, by this definition the ldo's dropout voltage is 0.5 v. dropout voltage is extremely critical to a linear regulator’s power efficiency. the lower the voltage allowable across a regulator while still maintaining a regulated output, the less power the regulator dissipates as a result. a low regulator dropout voltage is the key to this, as it takes a lower dropout to maintain regulation as the input voltage lowers. in performance terms, the bottom line for ldos is simply that more useful power is delivered to the load and less heat is generated in the regulator. ldos are key elements of power systems providing stable voltages from batteries, such as portable computers, cellular phones, etc. this is because they maintain a regulated output down to lower points on the battery’s discharge curve. or, within classic mains-powered raw dc supplies, ldos allow lower transformer secondary voltages, reducing system shutdowns under brownout conditions, as well as allowing cooler operation. some linear voltage regulator basics a brief review of three terminal linear ic regulator fundamentals is necessary before understanding the ldo variety. most (but not all) of the general three terminal regulator types available today are positive leg, series style regulators. this simply means that they control the regulated voltage output by means of a pass element in series with the positive unregulated input. and, although they are fewer in number, there are also negative leg series style regulators, which operate in a fashion complementary to the positive units. a basic hookup diagram of a three terminal regulator is shown in figure 9.53. in terms of basic functionality, many standard voltage regulators operate in a series mode, three- terminal form, just as shown here. as can be noted from this figure, the three i/o terminals are vin, gnd (or common), and vout. note also that this regulator block, in the absence of any assigned voltage polarity, could in principle be a positive type 9.66

hardware design techniques 9.3 analog power supply systems regulator. or, it might also be a negative style of voltage regulator—the principle is the same for both— a common terminal, as well as input and output terminals. in out three terminal regulator gnd iground (1ma) vin (6v) vmin = vin – vout = 1v vout (5v) il (1a) rl (5ω) common figure 9.53: a basic three terminal regulator hookup (either positive or negative) in operation, there are two power components which get dissipated in the regulator, one a function of vin – vout and il, plus a second which is a function of vin and iground. the first of these is usually dominant. analysis of the situation will reveal that as the dropout voltage vmin is reduced, the regulator is able to deliver a higher percentage of the input power to the load, and is thus more efficient, running cooler and saving power. this is the core appeal of the modern ldo type of regulator (see chapter 7 of this book and reference 1). a more detailed look within a typical regulator block diagram reveals a variety of elements, as is shown in figure 9.54. note that all regulators will contain those functional components connected via solid lines. the connections shown dotted indicate options, which might be available when more than three i/o pins are available. in operation, a voltage reference block produces a stable voltage vref, which is almost always a voltage based on the bandgap voltage of silicon, typically ~1.2 v (see reference 2). this allows output voltages of 3 v or more from supplies as low as 5 v. this voltage drives one input of an error amplifier, with the second input connected to the divider, r1- r2. the error amplifier drives the pass device, which in turn controls the output. the resulting regulated voltage is then simply: v out = v ref  +   1 r1 r2    . eq. 9.5 9.67

analog-digital conversion current limit pass device err overload saturation sensor overtemp sensor sd shutdown control vin vdropout = vmin = vin – vout vout iref r1 error amp vref vout vref = +  1 r r 1 2   r2 common figure 9.54: block diagram of a voltage regulator pass devices the pass device is a foremost regulator part, and the type chosen here has a major influence on almost all regulator performance issues. most notable among these is dropout voltage, vmin. analysis shows the use of an inverting mode pass transistor allows the pass device to be effectively saturated, thus minimizing the associated voltage losses. therefore this factor makes the two most desirable pass devices for ldo use a pnp bipolar, or a pmos transistor. these device types achieve the lowest levels of vin – vout required for ldo operation. in contrast, npn bipolars are poor as pass devices in terms of low dropout, particularly when they are darlington connected. standard fixed-voltage ic regulator architectures illustrate this point regarding pass devices. for example, the fixed-voltage lm309 5-v regulators and family derivatives such as the 7805, 7815 et. al., (and their various low and medium current alternates) are poor in terms of dropout voltage. these designs use a darlington pass connection, not known for low dropout (~1.5 v typical), or for low quiescent current (~5 ma). ±15-v regulator using adjustable voltage ics later developments in references and three-terminal regulation techniques led to the development of the voltage-adjustable regulator. the original ic to employ this concept was the lm317, a positive regulator. the device produces a fixed reference voltage of 1.25 v, appearing between the vout and adj pins of the ic. external scaling resistors set up the desired output voltage, adjustable in the range of 1.25-30 v. a complementary device, the lm337, operates in similar fashion, regulating negative voltages. 9.68

hardware design techniques 9.3 analog power supply systems an application example using standard adjustable three terminal regulators to implement a ±15-v linear power supply is shown in figure 9.55. this is a circuit as might be used for powering traditional op amp supply rails. it is capable of better line regulation performance than would an otherwise similar circuit, using standard fixed-voltage regulator devices, such as for example 7815 and 7915 ics. however, in terms of power efficiency it isn't outstanding, due to the use of the chosen ics, which require 2 v or more of headroom for operation. u1 u1 u1 lm317 lm317 lm317 in in in in in in out out out out out out adj adj adj com com com vin vin vin (unreg) (unreg) (unreg) c1 c1 c1 10µf 10µf 10µf c3 c3 c3 10µf 10µf 10µf (optional) (optional) (optional) vout= vref (1+ (r2/r1)) vout= vref (1+ (r2/r1)) vout= vref (1+ (r2/r1)) vref vref vref 1.25v 1.25v 1.25v r1 r1 r1 100ω 100ω 100ω d1 d1 1n4002 1n4002 r2 r2 r2 1.1kω 1.1kω 1.1kω c2 c2 c2 10µf 10µf 10µf vout vout vout 15v 15v 15v c6 c6 c6 10µf 10µf 10µf (optional) (optional) (optional) vin vin (unreg) (unreg) r4 r4 r4 1.1kω 1.1kω 1.1kω d2 d2 1n4002 1n4002 c4 c4 c4 10µf 10µf 10µf vref vref vref 1.25v 1.25v 1.25v r3 r3 r3 100ω 100ω 100ω adj adj adj com com com vout vout vout 15v 15v 15v c5 c5 c5 10µf 10µf 10µf in in in in in in out out out out out out u2 u2 u2 lm337 lm337 lm337 vout= vref (1+ (r4/r3)) vout= vref (1+ (r4/r3)) vout= vref (1+ (r4/r3)) figure 9.55: a classic ±15v, 1 a linear supply regulator using adjustable voltage regulator ics in the upper portion of this circuit an lm317 adjustable regulator is used, with r2 and r1 chosen to provide a 15-v output at the upper output terminal. if desired, r2 can easily be adjusted for other output levels, according to the figure's vout equation. resistor r1 should be left fixed, as it sets the minimum regulator drain of 10 ma or more. in this circuit, capacitors c1 and c2 should be tantalum types, and r1-r2 metal films. c3 is optional, but is highly recommended if the lowest level of output noise is desired. the normally reverse biased diode d1 provides a protective output clamp, for system cases where the output voltage would tend to reverse, if one supply should fail. the circuit operates from a rectified and filtered ac supply at vin, polarized as shown. the output current is determined by choosing the regulator ic for appropriate current capability. to implement the negative supply portion, the sister device to the lm317 is used, the lm337. the bottom circuit section thus mirrors the operation of the upper, delivering a negative 15v at the lowest output terminal. programming of the lm337 for output voltage is similar to that of the lm317, but uses resistors r4 and r3. r4 should be used to adjust the voltage, with r3 remaining fixed. c6 is again optional, but is recommended for reasons of lowest noise. 9.69

analog-digital conversion low dropout regulator architectures in contrast to traditional three terminal regulators with darlington or single-npn pass devices, low dropout regulators employ lower voltage threshold pass devices. this basic operational difference allows them to operate effectively down to a range of 100-200 mv in terms of their specified vmin. in terms of use within a system, this factor can have fairly significant operational advantages. an effective implementation of some key ldo features is contained in the analog devices series of anycap® ldo regulators. devices of this adp33xx series are so named for their relative insensitivity to the output capacitor, in terms of both its size and esr. available in power efficient packages such as the adi thermal coastline (and other thermally enhanced packages), they come in both stand-alone ldo and ldo controller forms (used with an external pmos fet). they also offer a wide span of fixed output voltages from 1.5 to 5 v, with rated current outputs up to 1500 ma. user- adjustable output voltage versions are also available. a basic simplified diagram for the family is shown schematically in figure 9.56. one of the key differences in the adp33xx ldo series is the use of a high gain vertical pnp pass device, q1, allowing typical dropout voltages for the series to be on the order of 1mv/ma for currents of 200 ma or less. vin q1q1 noninverting wideband driver ccomp + gm – ptat vos r3 d1 r1||r2 ×1 r4 iptat gnd vout r1 r2 cl rl figure 9.56: the adp33xx anycap® ldo architecture has both dc and ac performance advantages in circuit operation, vref is defined as a reference voltage existing at the output of a zero impedance divider of ratio r1/r2. in the figure, this is depicted symbolically by the (dotted) unity gain buffer amplifier fed by r1/r2, which has an output of vref. this reference voltage feeds into a series connection of (dotted) r1||r2, then actual components d1, r3, r4, etc. the regulator output voltage is: 9.70

hardware design techniques 9.3 analog power supply systems v out = v ref  +   1 r1 r2    . eq. 9.6 in the various devices of the adp33xx series, the r1-r2 divider is adjusted to produce standard output voltages of 1.5, 1.8, 2.5, 2.7, 2.75, 2.77, 2.85, 2.9, 3.0, 3.15, 3.2, 3.3, 3.6, and 5.0 v. the regulator behaves as if the entire error amplifier has simply an offset voltage of vref volts, as seen at the output of a conventional r1-r2 divider. while the above described dc performance enhancements of the adp33xx series are worthwhile, more dramatic improvements come in areas of ac-related performance. capacitive loading and the potential instability it brings is a major deterrent to easy ldo applications. one method of providing some measure of immunity to variation in an amplifier response pole is the use of a frequency compensation technique called pole splitting. in the figure 9.56 circuit, ccomp functions as the pole splitting capacitor, and provides benefits of a buffered, cl independent single-pole response. as a result, frequency response is dominated by the regulator’s internal compensation, and becomes relatively immune to the value and esr of load capacitor cl. this feature makes the design tolerant of virtually any output capacitor type. cl, the load capacitor, can be as low as 0.47 µf, and it can also be a multi-layer ceramic capacitor (mlcc) type, allowing a very small physical size for the entire regulation function. fixed-voltage, 50/100/200/500/1000/1500 ma ldo regulators a basic regulator application diagram common to various fixed voltage devices of the adp33xx device series is shown by figure 9.57. operation of the various pins and internal functions is discussed below. note that all pins and all functions are not available on all parts in the series, and individual data sheets should be consulted. this circuit is a general one, illustrating common points. for example, the adp33xx is a 50-ma basic ldo regulator device, designed for those fixed output voltages as noted. an actual adp3300 device ordered would be adp3300art-yy, where the "yy" is a voltage designator suffix such as 2.7, 3, 3.2, 3.3, or 5, for the respective table voltages. the "art" portion of the part number designates the package (sot23 6-lead). to produce 5v from the circuit, use the adp3300art-5. similar comments apply to the other devices, insofar as part numbering. for example, an adp3301ar-5 depicts an so-8 packaged 100-ma device, producing 5-v output. in operation, the circuit produces rated output voltage for loads under the max current limit, for input voltages above vout + vmin (where vmin is the dropout voltage for the specific device used, at rated current). the circuit is on when the shutdown input (if available on the particular device selected) is in a high state, either by a logic high control input to the sd pin, or by simply tying this pin to vin (shown dotted). when sd is low or grounded, the regulator shuts down, and draws a minimum quiescent current. 9.71

analog-digital conversion vin in nr anycap® ldo out (see table) sdsd gnd err c3 * vout r1 330kω output table output table device iout(ma) vout(v) device iout(ma) vout(v) adp3300 50 2.7, 3, 3.2, 3.3, 5 adp3300 50 2.7, 3, 3.2, 3.3, 5 adp3301 100 2.7, 3, 3.2, 3.3, 5 adp3301 100 2.7, 3, 3.2, 3.3, 5 adp3303 200 2.7, 3, 3.2, 3.3, 5 adp3303 200 2.7, 3, 3.2, 3.3, 5 adp3303a 200 adj. 2.2 - 10 adp3303a 200 adj. 2.2 - 10 c2 * 0.47 or 1µf c1 * 0.47 or 1µf on on off off * c1, c2, c3 values as per device data sheet note: multiple input / output pins, nr, sd, err, not available on all parts device iout(ma) vout(v) adp3307 adp3308 adp3309 adp3330 adp3331 adp3333 adp3334 adp3335 adp3336 adp3338 adp3339 100 2.7, 3, 3.2, 3.3 50 2.7, 2.85, 2.9, 3, 3.3, 3.6 100 2.7, 2.85, 2.9, 3, 3.3, 3.6 200 2.5, 2.75, 2.85, 3, 3.3, 3.6, 5 200 adj. 1.5 - 10 300 1.5, 1.8, 2.5, 2.77, 3, 3.15, 3.3, 5 500 adj. 1.5 - 10 500 1.8, 2.5, 2.85, 3.3, 5 500 adj. 1.5 - 10 1000 1.8, 2.5, 2.85, 3.3, 5 1500 1.8, 2.5, 2.85, 3.3, 5 figure 9.57: a basic ldo regulator hookup useful by device selection from 50 to 1500ma, at fixed or adjustable voltages per table the anycap regulator devices maintain regulation over a wide range of load, input voltage and temperature conditions. most devices have a combined error band of ±1.4% (or less). when an overload condition is detected, the open collector err goes to a low state (if available on the particular device selected). r1 is a pullup resistor for the err output. this resistor can be eliminated if the load provides a pullup current. c3, connected between the out and nr pins, can be used for an optional noise reduction (nr) feature (if available on the particular device selected). this is accomplished by bypassing a portion of the internal resistive divider, which reduces output noise ~10 db. when exercised, only the recommended low leakage capacitors as specific to a particular part should be used. the c1 input and c2 output capacitors should be selected as either 0.47 or 1-µf values respectively, again, as per the particular device used. for most devices of the series 0.47 µf suffices, but the adp3335 uses the 1-µf values. larger capacitors can also be used, and will provide better transient performance. heat sinking of device packages with more than 5 pins is enhanced, by use of multiple in and out pins. all of the pins available should therefore be used in the pcb design, to minimize layout thermal resistance. adjustable voltage, 200-ma ldo regulator in addition to the fixed output voltage ldo devices discussed above, adjustable versions are also available, to realize non-standard voltages. the adp3331 is one such device, and it is shown in figure 9.58, configured as a 2.8-v output, 200-ma ldo application. 9.72

hardware design techniques 9.3 analog power supply systems vin in errerr c1 0.47µf on on off off adp3331 out sdsd gnd fb r3 330kω r1 536kω r2 402kω vout = 2.8v c2 0.47µf figure 9.58: an adjustable 200ma ldo regulator set up for a 2.8-v output the adp3331 is generally similar to other anycap ldo parts, with two notable exceptions. it has a lower quiescent current (~34 µa when lightly loaded) and most importantly, the output voltage is user-adjustable. as noted in the circuit, r1 and r2 are external precision resistors used to define the regulator operating voltage. the output of this regulator is vout, which is related to feedback pin fb voltage vfb as: v out v= fb  +   1 r1 r2    , eq. 9.7 where vfb is 1.204 v. resistors r1 and r2 program vout, and their parallel equivalent should be kept close to 230 kω for best stability. to select r1 and r2, first calculate their ideal values, according to the following two expressions: =r1   230   v out v fb   ωk  =r2 ωk 230   1   + v fb v out     eq. 9.8 eq. 9.9 in the example circuit, vout is 2.8 v, which yields r1 = 534.9 kω, and r2 = 403.5 kω. as noted in the figure, closest standard 1% values are used, which provides an output of 2.8093 v (perfect resistors assumed). in practice, the resistor tolerances should be added to the ±1.4% tolerance of the adp3331 for an estimation of overall error. to complement the above-discussed anycap series of standalone ldo regulators, there is the ldo regulator controller. the regulator controller ic picks up where the standalone regulator stops for either load current or power dissipation, using an external pmos fet pass device. as such, the current capability of the ldo can be extended to several amps. an ldo regulator controller application is shown later in this discussion. 9.73

analog-digital conversion these application examples above illustrate a subset of the entire anycap family of ldos. further information on this series of standalone and regulator controller ldo devices can be found in the references at the end of the section. charge-pump voltage converters another method for developing supply voltage for op amp systems employs what is known as a charge-pump circuit (also called switched capacitor voltage conversion). charge-pump voltage converters accomplish energy transfer and voltage conversion using charges stored on capacitors, thus the name, charge-pump. using switching techniques, charge-pumps convert supply voltage of one polarity to a higher or lower voltage, or to an alternate polarity (at either higher or lower voltage). this is accomplished with only an array of low resistance switches, a clock for timing, and a few external storage capacitors to hold the charges being transferred in the voltage conversion process. no inductive components are used, thus emi generation is kept to a minimum. although relatively high currents are switched internally, the high current switching is localized, and therefore the generated noise is not as great as in inductive type switchers. with due consideration towards component selection, charge-pump converters can be implemented with reasonable noise performance. the two common charge-pump voltage converters are the voltage inverter and the voltage doubler circuits. in a voltage inverter, a charge pump capacitor is charged to the input voltage during the first half of the switching cycle. during the second half of the switching cycle the input voltage stored on the charge pump capacitor is inverted, and is applied to an output capacitor and the load. thus the output voltage is essentially the negative of the input voltage, and the average input current is approximately equal to the output current. the switching frequency impacts the size of the external capacitors required, and higher switching frequencies allow the use of smaller capacitors. the duty cycle—defined as the ratio of charge pump charging time to the entire switching cycle time—is usually 50%, which yields optimal transfer efficiency. a voltage doubler works similarly to the inverter. in this case the pump capacitor accomplishes a voltage doubling function. in the first phase it is charged from the input, but in the second phase of the cycle it appears in series with the output capacitor. over time, this has the effect of doubling the magnitude of the input voltage across the output capacitor and load. both the inverter and voltage doubler circuits provide no voltage regulation in basic form. however, techniques exist to add regulation (discussed below). there are advantages and disadvantages to using charge-pump techniques, compared to inductor-based switching regulators. an obvious key advantage is the elimination of the inductor and the related magnetic design issues. in addition, charge-pump converters typically have relatively low noise and minimal radiated emi. application circuits are simple, and usually only two or three external capacitors are required. because there are no inductors, the final pcb height can generally be made smaller than a comparable inductance-based switching regulator. charge-pump inverters are also low in cost, compact, and capable of efficiencies greater than 90%. obviously, current output is 9.74

hardware design techniques 9.3 analog power supply systems limited by the capacitor size and the switch capacity. typical ic charge-pump inverters have 150-ma maximum outputs. on their downside, charge-pump converters don't maintain high efficiency for a wide voltage range of input to output, unlike inductive switching regulators. nevertheless, they are still often suitable for lower current loads where any efficiency disadvantages are a small portion of a larger system power budget. a summary of general charge-pump operating characteristics is shown in figure 9.59. (cid:139) no inductors! (cid:139) minimal radiated emi (cid:139) simple implementation: 2 external capacitors, 1 diode (for doubler), input capacitor (cid:139) efficiency > 90% achievable (cid:139) low cost, compact, low profile (height) (cid:139) optimized for inverting or doubling supply voltage with output regulation: adp3605, adp3607 (cid:139) inverter/triplers with three outputs from +3v input: adm8830, adm8839, adm8840 figure 9.59: some general charge-pump characteristics an example of charge-pump applicability is the voltage inverter function. inverters are often useful where a relatively low current negative voltage (i.e., –3 v) is required, in addition to a primary positive voltage (such as 5 v). this may occur in a single supply system, where only a few high performance parts require the negative voltage. similarly, voltage doublers (and triplers) are useful in low current applications, where a voltage greater than a primary supply voltage is required. both regulated and unregulated charge pump voltage inverters and doublers are available depending upon the particular application. regulated output charge-pump voltage converters adding regulation to a simple charge-pump voltage converter function greatly enhances its usefulness for most applications. there are several techniques for adding regulation to a charge-pump converter. the most straightforward is to follow the charge-pump inverter/doubler with an ldo regulator. the ldo provides the regulated output, and can also reduce the charge-pump converter's ripple. this approach, however, adds complexity and reduces the available output voltage by the dropout voltage of the ldo (~200 mv). these factors may or may not be a disadvantage. by far the simplest and most effective method for achieving regulation in a charge-pump voltage converter is to simply use a charge-pump design with an internal error amplifier, to control the on-resistance of one of the switches. 9.75

analog-digital conversion this method is used in the adp3605 voltage inverter and the adp3607 voltage doubler, devices offering regulated outputs for positive input voltage ranges. the output is sensed and fed back into the device via a sensing pin, vsense. key features of the series are good output regulation, 5% in the adp3605, and a high switching frequency of 250 khz, good for both high efficiency and small component size. an simplified functional diagram of the adp3607 voltage doubler ic from this series is shown in figure 9.60. the application circuit shown in figure 9.61 is a 3-v to 5-v doubler, with the output regulated ±5% for currents up to 50 ma. in normal operation, the shutdown pin is connected to ground. alternately, a logic high at this pin shuts the device down to a standby current of 150 µa. 3v - 5v 5v figure 9.60: adp3607 regulated 5-v, 50-ma output charge pump doubler the capacitors for cin, cp, and co should have esrs of less than 150 mω and should be 10 µf. however, 4.7 µf can be used at the expense of slightly higher output ripple voltage. cp is the most critical of the three, because of its higher current flow. the tantalum type listed is recommended for lowest output ripple. with values as shown, typical output ripple voltage ranges up to approximately 30 mv as the output current varies over the 50-ma range. these application examples illustrate a subset of the entire charge-pump ic family. other charge pumps are available, including regulated charge pumps specifically for tft displays with three output voltages (+5 v, +15 v, and –15 v) are available. for further information on these and other devices consult http://www.analog.com. 9.76

hardware design techniques 9.3 analog power supply systems 3v - 5v figure 9.61: adp3607-5 charge pump application circuit linear post regulator for switching supplies another powerful noise reduction option which can be utilized in conjunction with a switching type supply is the option of a linear post regulator stage. this is at best an ldo type of regulator, chosen for the desired clean analog voltage level and current. it is preceded by a switching stage, which might be a buck or boost type inductor-based design, or it may also be a charge-pump. the switching converter allows the overall design to be more power-efficient, and the linear post regulator provides clean regulation at the load, reducing the noise of the switcher. this type of regulator can also be termed hybrid regulation, since it combines both switching and linear regulation concepts. an example circuit is shown in figure 9.62, which features a 3.3-v/1-a low noise, analog-compatible regulator. it operates from a nominal 9v supply, using a buck or step- down type of switching regulator, as the first stage at the left. the switcher output is set for a few hundred mv above the desired final voltage output, minimizing power in the ldo stage at the right. this feature may eliminate need for a heat sink on the ldo pass device. in this example the 1148 ic switcher is set up for a 3.75-v output by r1-r2, but in principle, this voltage can be anything suitable to match the headroom of the companion ldo (within specification limits, of course). in addition, the principle extends to any ldo devices and other current levels, and other switching regulators. the adp3310-3.3 is a fixed-voltage ldo controller, driving a pmos fet pass device, with a 3.3-v output. the linear post regulation stage provides both noise-reduction (in this case about 14 db), as well as good dc regulation. to realize best results, good grounding practices must be followed. in tests, noise at the 3.3-v output was about 5 mv p-p at the 150-khz switcher 9.77

analog-digital conversion frequency. note that the ldo noise rejection for such relatively high frequencies is much less than at 100/120 hz. note also that c2's esr will indirectly control the final noise output. the ripple figures given are for a general-purpose c2 part, and can be improved. 3.75v output 3.75v output switching switching regulator regulator vin vin 9v 9v 10nf 10nf vin vin irf7204 irf7204 int vcc int vcc 3.3v output 3.3v output ldo linear ldo linear regulator regulator ifr7404 ifr7404 1µf 1µf 220µf 220µf + + 35v 35v c1 c1 3.75v 3.75v p-ch p-ch l, 68µh l, 68µh rsense rsense 0.1ω 0.1ω p-drive p-drive 1148 1148 sense (+) sense (+) sd sd ith ith ct ct sense (–) sense (–) 1000pf 1000pf n-drive n-drive sgnd sgnd fb fb pgnd pgnd irf7403 irf7403 n-ch n-ch 10bq040 10bq040 + + c2 c2 100µf 100µf 20v 20v in in gate gate out out adp3310-3.3 adp3310-3.3 gnd gnd 3.3v 3.3v 1a 1a + + c3 c3 10µf 10µf 35v 35v r1 r1 20kω 20kω r2 r2 10kω 10kω cc cc 2200pf 2200pf rc, 1kω rc, 1kω ct ct 470pf 470pf figure 9.62: a linear post-regulator operating after a switching/linear regulator is capable of low noise, as well as good dc efficiency grounding linear and switching regulators the importance of maintaining a low impedance large area ground plane is critical to practically all analog circuits today, especially high current low dropout linear regulators or switching regulators. the ground plane not only acts as a low impedance return path for high frequency switching currents but also minimizes emi/rfi emissions. in addition, it serves to minimize unwanted voltage drops due to high load currents. because of the shielding action of the ground plane, the circuit's susceptibility to external emi/rfi is also reduced. when using multilayer pc boards, it is wise to add a power plane. in this way, low impedances can be maintained on both critical layers. figure 9.63 shows a grounding arrangement for a low dropout linear regulator such as the adp3310. it is important to minimize the total voltage drop between the input voltage and the load, as this drop will subtract from the voltage dropped across the pass transistor and reduce its headroom. for this reason, these runs should be wide, heavy traces and are indicated by the wide interconnection lines on the diagram. the low-current ground (gnd) and vout (sense) pins of the adp3310 are connected directly to the load so that the regulator regulates the voltage at the load rather than at its own output. the is and vin connections to the rs current sense resistor should be made directly to the resistor terminals to minimize parasitic resistance, since the current limit resistor is typically a very low value (milliohms). in fact, for very low values it may actually consist of a pc board trace of the proper width, length, and thickness to yield the desired resistance. 9.78

vin rs hardware design techniques 9.3 analog power supply systems is gate vin adp3310 ldo vout linear reg. controller gnd load c2 c1 power common (cid:206) short connection to ground plane (cid:206) short heavy traces figure 9.63: grounding and signal routing techniques for low dropout regulators method 1 the input decoupling capacitor (c1) should be connected with short leads at the regulator input in order to absorb any transients which may couple onto the input voltage line. similarly, the load capacitor (c2) should have minimum lead length in order to absorb transients at that point and prevent them from coupling back into the regulator. the single-point connection to the low impedance ground plane is made directly at the load. figure 9.64 shows a grounding arrangement which is similar to that of figure 9.63 with the exception that all ground connections are made with direct connections to the ground plane. this method works extremely well when the regulator and the load are on the same pc board, and the load is distributed around the board rather than located at one specific point. if the load is not distributed, the connection from vout (sense) should be connected directly to the load as shown by the dotted line in the diagram. this ensures the regulator provides the proper voltage at the load regardless of the drop in the trace connecting the pass transistor output to the load. switching regulators present major challenges with respect to layout, grounding, and filtering. the discussion above on linear regulators applies equally to switchers, although the importance of dc voltage drops may not be as great. there is no way to eliminate high frequency switching currents in a switching regulator, since they are necessary for the proper operation of the regulator. what one must do, however, is to recognize the high switching current paths and take proper measures to ensure that they do not corrupt circuits on other parts of the board or system. figure 9.65 shows a generic synchronous switching regulator controller ic and the associated external mosfet switching transistors. the heavy bold lines indicate the paths where 9.79

hardware design techniques 9.3 analog power supply systems in order to minimize stray inductance and resistance, each of the high current paths should be as short as possible. capacitors c1 and c2a must absorb the bulk of the input and output switching current and shunt it to the single-point ground. any additional resistance or inductance in series with these capacitors will degrade their effectiveness. minimizing the area of all the loops containing the switching currents prevents them from significantly affecting other parts of the circuit. in actual practice, however, the single- point concept in figure 9.65 is difficult to implement without adding additional lead length in series with the various components. the added lead length required to implement the single-point grounding scheme tends to degrade the effects of using the single-point ground in the first place. a more practical solution is to make multiple connections to the ground plane and make each of them as short as possible. this leads to the arrangement shown in figure 9.66, where each critical ground connection is made directly to the ground plane with the shortest connection length possible. by physically locating all critical components associated with the regulator close together and making the ground connections short, stray series inductance and resistance are minimized. it is true that several small ground loops may occur using this approach, but they should not cause significant system problems because they are confined to a very small area of the overall large-area ground plane. vin vcc c1 switching regulator controller sgnd pgnd power common c2a load c2b (cid:206) short connection to ground plane (cid:206) short heavy traces figure 9.66: grounding and signal routing techniques for switching regulators method 2 power supply noise reduction and filtering during the last decade or so, switching power supplies have become much more common in electronic systems. as a consequence, they also are being used for analog supplies. good reasons for the general popularity include their high efficiency, low temperature rise, small size, and light weight, as opposed to equivalent-power linear regulators. 9.81

analog-digital conversion in spite of these benefits, switchers do have drawbacks, most notably high output noise. this noise generally extends over a broad band of frequencies, resulting in both conducted and radiated noise, as well as unwanted electric and magnetic fields. voltage output noise of switching supplies are short-duration voltage transients, or spikes. although the fundamental switching frequency can range from 20 khz to 1 mhz, the spikes can contain frequency components extending to 100 mhz or more. while specifying switching supplies in terms of rms noise is common vendor practice, as a user you should also specify the peak (or peak-to-peak) amplitudes of the switching spikes, with the output loading of your system. this section discusses filter techniques for rendering a switching regulator output analog ready, that is sufficiently quiet to power precision op amp and other analog circuitry with relatively small loss of dc terminal voltage. the filter solutions presented are generally applicable to all power supply types incorporating switching element(s) in their energy path. this includes charge-pump as well as other switching type converters and supplies. this section focuses on reducing conducted type switching power supply noise with external post filters, as opposed to radiated type noise. tools useful for combating high frequency switcher noise are shown by figure 9.67. these differ in electrical characteristics as well as practicality towards noise reduction, and are listed roughly in an order of priorities. of these tools, l and c are the most powerful filter elements, and are the most cost-effective, as well as small in size. (cid:139) capacitors (cid:139) inductors (cid:139) ferrites (cid:139) resistors (cid:139) linear post regulation (cid:139) proper layout and grounding (cid:139) physical separation! figure 9.67: tools useful in reducing power supply noise capacitors capacitors are probably the single most important filter component for reducing switching-related noise. as noted in the first section of this chapter, there are many different types of capacitors. it is also quite true that understanding of their individual characteristics is absolutely mandatory to the design of effective and practical power supply filters. there are generally three classes of capacitors useful in 10-khz to 100-mhz filters, broadly distinguished as the generic dielectric types; electrolytic, film, and ceramic. these discussions complement earlier ones, focusing on power-related concepts. with any dielectric, a major potential filter loss element is esr (equivalent series resistance), the net parasitic resistance of the capacitor. esr provides an ultimate limit to 9.82

hardware design techniques 9.3 analog power supply systems filter performance, and requires more than casual consideration, because it can vary both with frequency and temperature in some types. another capacitor loss element is esl (equivalent series inductance). esl determines the frequency where the net impedance characteristic switches from capacitive to inductive. this varies from as low as 10 khz in some electrolytics to as high as 100 mhz or more in chip ceramic types. both esr and esl are reduced when a leadless package is used. all capacitor types mentioned are available in surface mount packages, preferable for high speed uses. the electrolytic family provides an excellent, cost-effective low-frequency filter component, because of the wide range of values, a high capacitance-to-volume ratio, and a broad range of working voltages. it includes general purpose aluminum electrolytic types, available in working voltages from below 10 v up to about 500 v, and in size from 1 to several thousand µf (with proportional case sizes). all electrolytic capacitors are polarized, and cannot withstand more than a volt or so of reverse bias without damage. a subset of the general electrolytic family includes tantalum types, generally limited to voltages of 100 v or less, with capacitance of 500 µf or less (see reference 7). in a given size, tantalums exhibit a higher capacitance-to-volume ratios than do general purpose electrolytics, and have both a higher frequency range and lower esr. they are generally more expensive than standard electrolytics, and must be carefully applied with respect to surge and ripple currents. a subset of aluminum electrolytic capacitors is the switching type, designed for handling high pulse currents at frequencies up to several hundred khz with low losses (see reference 8). this capacitor type can compete with tantalums in high frequency filtering applications, with the advantage of a broader range of values. a more specialized high performance aluminum electrolytic capacitor type uses an organic semiconductor electrolyte (see reference 9). the os-con capacitors feature appreciably lower esr and higher frequency range than do other electrolytic types, with an additional feature of minimal low-temperature esr degradation. film capacitors are available in very broad value ranges and an array of dielectrics, including polyester, polycarbonate, polypropylene, and polystyrene. because of the low dielectric constant of these films, their volumetric efficiency is quite low, and a 10-µf/50-v polyester capacitor (for example) is actually a handful. metalized (as opposed to foil) electrodes does help to reduce size, but even the highest dielectric constant units among film types (polyester, polycarbonate) are still larger than any electrolytic, even using the thinnest films with the lowest voltage ratings (50 v). where film types excel is in their low dielectric losses, a factor which may not necessarily be a practical advantage for filtering switchers. for example, esr in film capacitors can be as low as 10 mω or less, and the behavior of films generally is very high in terms of q. in fact, this can cause problems of spurious resonance in filters, requiring damping components. as typically constructed using wound layers, film capacitors can be inductive, which limits their effectiveness for high frequency filtering. obviously, only non-inductively made film caps are useful for switching regulator filters. one specific style which is non- inductive is the stacked-film type, where the capacitor plates are cut as small overlapping 9.83

analog-digital conversion linear sheet sections from a much larger wound drum of dielectric/plate material. this technique offers the low inductance attractiveness of a plate sheet style capacitor with conventional leads (see references 8 and 10). obviously, minimal lead length should be used for best high frequency effectiveness. very high current polycarbonate film types are also available, specifically designed for switching power supplies, with a variety of low inductance terminations to minimize esl (see reference 11). dependent upon their electrical and physical size, film capacitors can be useful at frequencies to above 10 mhz. at the highest frequencies, only stacked film types should be considered. leadless surface mount packages are now available for film types, minimizing inductance. ceramic is often the capacitor material of choice above a few mhz, due to its compact size, low loss, and availability up to several µf in the high-k dielectric formulations (x7r and z5u), at voltage ratings up to 200 v (see ceramic families of reference 7). multilayer ceramic "chip caps" are very popular for bypassing and/or filtering at 10 mhz or more, simply because their very low inductance design allows near optimum rf bypassing. for smaller values, ceramic chip caps have an operating frequency range to 1 ghz. for high frequency applications, a useful selection can be ensured by selecting a value which has a self-resonant frequency above the highest frequency of interest. the capacitor model and waveforms of figure 9.68 illustrate how the various parasitic model elements become dominant, dependent upon the operating frequency. assume an input current pulse changing from 0 to 1 a in 100 ns, as noted in the figure, and consider what voltage will be developed across the capacitor. i ipeak = 1a v input current di dt = 1 a 100 ns equivalent f = 3.5mhz output voltage vpeak esl = • + esr ipeak • di dt = 400 m v esr (cid:149) ipeak = 200mv esr = 0.2ω esl = 20nh c = 100µf xc = 0.0005ω @ 3.5mhz 0 0 figure 9.68: capacitor equivalent circuit and response to input current pulse the fast-rising edge of the current waveform shown results in an initial voltage peak across the capacitor, which is proportional to the esl. after the initial transient, the voltage settles down to a longer duration level which is proportional to the esr of the capacitor. thus the esl determines how effective a filter the capacitor is for the fastest 9.84

hardware design techniques 9.3 analog power supply systems components of the current signal, and the esr is important for longer time frame components. note that an overall time frame of a few microseconds (or even less) is relevant here. as things turn out, this means switching frequencies in the 100-khz to 1-mhz range. unfortunately however, this happens to be the region where most electrolytic types begin to perform poorly. all electrolytics will display impedance curves similar in general shape to that of figure 9.69. in a practical capacitor, at frequencies below about 10 khz the net impedance seen at the terminals is almost purely capacitive (c region). at intermediate frequencies, the net impedance is determined by esr, for example about 0.1 to 0.5 ω at ~125 khz, for several types (esr region). above about several hundred khz to 1 mhz these capacitor types become inductive, with net impedance rising (esl region). c (100µf) region esl (20nh) region log |z| esr (0.2ω) region esr = 0.2ω 10khz 1mhz log frequency figure 9.69: electrolytic capacitor impedance versus frequency the minimum impedance within the 10 khz to 1 mhz range will vary with the magnitude of the capacitor's esr. this is the primary reason why esr is the most critical item in determining a given capacitor’s effectiveness as a switching supply filter element. higher up in frequency, the inductive region will vary with esl (which in turn is also strongly effected by package style). it should go without saying that a wideband impedance plot for a capacitor being considered for a filter application will go a long way towards predicting its potential value, as well as for comparing one type against another. it should be understood that all real world capacitors have some finite esr. while it is usually desirable for filter capacitors to possess low esr, this isn't always so. in some cases, the esr may actually be helpful in reducing resonance peaks in filters, by supplying "free" damping. for example, in most electrolytic types, a nominally flat broad series resonance region can be noted in an impedance vs. frequency plot. this occurs where |z| falls to a minimum level, nominally equal to the capacitor's esr at that frequency. this low q resonance can generally be noted to cover a relatively wide frequency range of several octaves. contrasted to the high q sharp resonances of film and ceramic caps, electrolytic's low q behavior can be useful in controlling resonant peaks. 9.85

analog-digital conversion ferrites a second important filter element is the inductor, available in various forms. the use of ferrite core materials is prevalent in inductors most practical for power supply filtering. regarding inductors, ferrites, which are non-conductive ceramics manufactured from the oxides of nickel, zinc, manganese, etc., are extremely useful in power supply filters (see reference 12). ferrites can act as either inductors or resistors, dependent upon their construction and the frequency range. at low frequencies (<100 khz), inductive ferrites are useful in low-pass lc filters. at higher frequencies, ferrites become resistive, which can be an important characteristic in high-frequency filters. again, exact behavior is a function of the specifics. ferrite impedance depends on material, operating frequency range, dc bias current, number of turns, size, shape, and temperature. figure 9.70 summarizes a number of ferrite characteristics. (cid:139) ferrites good for frequencies above 25khz (cid:139) many sizes / shapes available including leaded "resistor style" (cid:139) ferrite impedance at high frequencies primarily resistive -- ideal for hf filtering (cid:139) low dc loss: resistance of wire passing through ferrite is very low (cid:139) high saturation current versions available (cid:139) choice depends upon: (cid:122) source and frequency of interference (cid:122) impedance required at interference frequency (cid:122) environmental: temperature, ac and dc field strength, size and space available (cid:139) always test the design! figure 9.70: a summary of ferrite characteristics several ferrite manufacturers offer a wide selection of ferrite materials from which to choose, as well as a variety of packaging styles for the finished network (see references 13 and 14). a simple form is the bead of ferrite material, a cylinder of the ferrite which is simply slipped over the power supply lead to the decoupled stage. alternately, the leaded ferrite bead is the same bead, pre-mounted on a length of wire and used as a component (see reference 14). more complex beads offer multiple holes through the cylinder for increased decoupling, plus other variations. surface mount beads are also available. pspice models of fair-rite ferrites are available, allowing ferrite impedance estimations (see reference 15). the models match measured rather than theoretical impedances. a ferrite's impedance is dependent upon a number of inter-dependent variables, and is difficult to quantify analytically, thus selecting the proper ferrite is not straightforward. however, knowing the following system characteristics will make selection easier. first, determine the frequency range of the noise to be filtered. second, the expected temperature range of the filter should be known, as ferrite impedance varies with temperature. third, the dc current flowing through the ferrite must be known, to ensure that the ferrite does not saturate. although models and other analytical tools may prove 9.86

hardware design techniques 9.3 analog power supply systems useful, the general guidelines given above, coupled with actual filter experimentation connected under system load conditions, should lead to a proper ferrite selection. card entry filter using proper component selection, low and high frequency band filters can be designed to smooth a noisy switching supply output so as to produce an analog ready supply. it is most practical to do this over two (and sometimes more) stages, each stage optimized for a range of frequencies. a basic stage can be used to carry the entire load current, and filter noise by 60 db or more up to a 1- to 10-mhz range. figure 9.71 illustrates this type of filter, which is used as a card entry filter, providing broadband filtering for all power entering a pc card. + 3-5v noisy input from switching supply or dc-dc converter l1 * 100µh c1 100µf/20v tantalum + c2 1µf ceramic * fastron mesc series or equivalent r1 1ω - + 3-5v clean output to 300ma load analog stage - figure 9.71: a card-entry filter is useful for low-medium frequency power line noise filtering in analog systems in this filter, l1 and c1 perform the primary filtering, which provides a corner frequency of about 1.6 khz. with the corner thus placed well below typical switching frequencies, the circuit can have good attenuation up to 1 mhz, where the typical attenuation is on the order of 60 db. at higher frequencies parasitics limit performance, and a second filter stage will be more useful. the ultimate level of performance available from this filter will be related to the components used within it. l1 should be derated for the operating current, thus for 300-ma loads it is a 1-a type. the specified l1 choke has a typical dc resistance of 0.65 ω, for low drop across the filter (see reference 16). c1 can be either a tantalum or an aluminum electrolytic, with moderately low esr. for current levels lower than 300 ma, l1 can be proportionally downsized, saving space. the resistor r1 provides damping for the lc filter, to prevent possible ringing. r1 can be reduced or even possibly eliminated, if the esr of c1 provides a comparable impedance. 9.87

analog-digital conversion while the example shown is a single-supply configuration, obviously the same filter concepts apply for dual supplies. rail bypass/distribution filter a complement to the card-entry filter is the rail-bypass filter scheme of figure 9.72. when operating from relatively clean power supplies, the heavy noise filtering of the card entry filter may not be necessary. however, some sort of low frequency bypassing with appreciable energy storage is almost always good, and this is especially true if high currents are being delivered by the stages under power. card connector +vs rail input common (gnd) input -vs rail input #1 #2 #3 to individual stage +vs rail c1 100µf/ 25v multiple pin contacts ground plane c2 100µf/ 25v #1 #2 #3 to individual stage -vs rail figure 9.72: dual-supply low frequency rail bypass/distribution filter in such cases, some lumped low frequency bypassing is appropriate on the card. although these energy storage filters need not be immediately adjacent to the ics they serve, they should be within a few inches. this type of bypassing scheme should be considered a minimum for powering any analog circuit. the exact capacitor values aren't critical, and can vary appreciably. the most important thing is to avoid leaving them out! the circuit shown uses c1 and c2 as these bypasses in a dual-rail system. note that multiple card contacts are recommended for the i/o pins, especially ground connection. from the capacitors outward, supply rail traces are distributed to each stage as shown, in "star" distribution fashion. note—while this is the optimum method to minimize inter- stage crosstalk, in practice some degree of "daisy chaining" is often difficult to avoid. a prudent designer should therefore carefully consider common supply currents effects in designing these pcb distribution paths. wider than normal traces are recommended for these supply rails, especially those carrying appreciable current. if the current levels are in the ampere region, then star-type supply distribution with ultra-wide traces should be considered mandatory. in extreme cases, a dedicated power plane can be used. the impedance of the ground return path is minimized by the use of a ground plane. 9.88

hardware design techniques 9.3 analog power supply systems local high frequency bypass/decoupling at each individual analog stage, further local, high-frequency-only filtering is used. with this technique, used in conjunction with either the card-entry filter or the low frequency bypassing network, such smaller and simpler local filter stages provide optimum high frequency decoupling. these stages are provided directly at the power pins, of all individual analog stages. figure 9.73 shows this technique, in both correct (left) as well as incorrect example implementations (right). in the left example, a typical 0.1-µf chip ceramic capacitor goes directly to the opposite pcb side ground plane, by virtue of the via, and on to the ic's gnd pin by a second via. in contrast, the less desirable setup at the right adds additional pcb trace inductance in the ground path of the decoupling cap, reducing effectiveness. correct incorrect optional ferrite beads power supply trace decoupling capacitor power supply trace decoupling capacitor v+ ic gnd vias to ground plane v+ ic gnd pcb trace via to ground plane figure 9.73: localized high frequency supply filter(s) provides optimum filtering and decoupling via short low-inductance path (ground plane) the general technique is shown here as suitable for a single-rail power supply, but the concept obviously extends to dual rail systems. note—if the decoupled ic in question is an op amp, the gnd pin shown is the –vs pin. for dual supply op amp uses, there is no op amp gnd pin per se, so the dual decoupling networks should go directly to the ground plane when used, or other local ground. all high frequency (i.e., ≥10 mhz) ics should use a bypassing scheme similar to figure 9.73 for best performance. trying to operate op amps and other high performance ics without local bypassing is almost always folly. it may be possible in a few circumstances, if the circuitry is strictly micropower in nature, and the gain-bandwidth in the khz range. to put things into an overall perspective however, note that a pair of 0.1-µf ceramic bypass caps cost less than 25 cents. hardly a worthy saving compared to the potential grief and lost time of troubleshooting a system without bypassing! in contrast, the ferrite beads aren't 100% necessary, but they will add extra high frequency noise isolation and decoupling, which is often desirable. possible caveats here 9.89

hardware design techniques 9.3 analog power supply systems references: 9.3 analog power supply systems 1. walt jung, "references and low dropout linear regulators," section 2 within walt kester, ed., practical design techniques for power and thermal management, analog devices, inc., 1998, isbn 0-916550-19-2. 2. paul brokaw, "a simple three-terminal ic bandgap voltage reference," ieee journal of solid state circuits, vol. sc-9, december, 1974. 3. frank goodenough, "vertical-pnp-based monolithic ldo regulator sports advanced features," electronic design, may 13, 1996. 4. frank goodenough, "low dropout regulators get application specific," electronic design, may 13, 1996. 5. walt kester, brian erisman, gurgit thandi, "switched capacitor voltage converters," section 4 within walt kester, editor, practical design techniques for power and thermal management, analog devices, inc., 1998, isbn 0-916550-19-2. 6. walt jung, walt kester, bill chesnut, "power supply noise reduction and filtering," portion of section 8 within walt kester, editor, practical design techniques for power and thermal management, analog devices, inc., 1998, isbn 0-916550-19-2. 7. tantalum electrolytic and ceramic capacitor families, kemet electronics, box 5928, greenville, sc, 29606, (803) 963-6300. 8. type hfq aluminum electrolytic capacitor and type v stacked polyester film capacitor, panasonic, 2 panasonic way, secaucus, nj, 07094, (201) 348-7000. 9. os-con aluminum electrolytic capacitor technical book, sanyo, 3333 sanyo road, forrest city, ak, 72335, (501) 633-6634. 10. ian clelland, "metallized polyester film capacitor fills high frequency switcher needs," pcim, june 1992. 11. type 5mc metallized polycarbonate capacitor, electronic concepts, inc., box 1278, eatontown, nj, 07724, (908) 542-7880. 12. henry w. ott, noise reduction techniques in electronic systems, 2nd edition, john wiley, inc., 1988, isbn: 0-471-85068-3. 13. fair-rite linear ferrites catalog, fair-rite products, box j, wallkill, ny, 12886, (914) 895-2055. 14. type excel leaded ferrite bead emi filter, and type exc l leadless ferrite bead, panasonic, 2 panasonic way, secaucus, nj, 07094, (201) 348-7000. 15. steve hageman, "use ferrite bead models to analyze emi suppression," the design center source, microsim newsletter, january, 1995. 16. "mesc series rfi suppression chokes," fastron gmbh, zum kaiserblick 25, 83620 feldkirchen- westerham, germany, www.fastron.de 9.91

hardware design techniques 9.4 overvoltage protection section 9.4: overvoltage protection walt jung, walt kester, james bryant, joe buxton, wes freeman frequently, data converters, op amps, and other analog ics require protection against destructive potentials at their input and output terminals. one basic reason behind this is that these ics are by nature relatively fragile components. although designed to be as robust as possible for normal signals, there are nevertheless certain application and/or handling conditions where they can see voltage transients beyond their ratings. this situation can occur for either of two instances. the first of these is in-circuit, that is, operating within an application circuit. the second instance is out-of-circuit, which might be at anytime after receipt from a supplier, but prior to final assembly and mounting of the ic. in either case, under overvoltage conditions, it is a basic fact-of-life that unless the designer limits the fault currents at the input (or possibly output) of the ic, it can be damaged or destroyed. so, obviously the designer should fully understand all of the fault mechanisms internal to those ics that may require protection. this then allows design of networks that can protect the in-circuit ic throughout its lifetime, without undue compromise of speed, precision, etc. or, for the out-of-circuit ic, it can help define proper protective handling procedures until it reaches its final destination. this section of the chapter examines a variety of protection schemes to ensure adequate protection for op amps and other analog ics for in-circuit applications, as well as for out-of-circuit environments. in-circuit overvoltage protection there are many common cases that stress op amps and other analog ics at the input, while operating within an application, i.e., in-circuit. since these ics must often interface to the outside world, this may entail handling voltages exceeding their absolute maximum ratings. for example, sensors are often placed in environments where a fault condition can expose the circuit to a dangerously high voltage. with the sensor connected to a signal processing amplifier, the input then sees excessive voltages during a fault. general input common mode limitations whenever the op amp or data converter input common-mode (cm) voltage goes outside its supply range, the device can be damaged, even if the supplies are turned off. accordingly, the absolute maximum input ratings of almost all linear ics limits the greatest applied voltage to a level equal to the positive and negative supply voltage, plus about 0.3 v beyond these voltages (i.e., +vs + 0.3 v, or –vs – 0.3 v). while some exceptions to this general rule might exist it is important to note this: most linear ics require input protection when overvoltage of more than 0.3 v beyond the rails occurs. a safe operating rule is to always keep the applied cm voltage between the rail limits. here, "safe" implies prevention of outright ic destruction. as will be seen later, there are also intermediate "danger-zone" cm conditions between the rails with certain devices, which can invoke dangerous (but not necessarily destructive) behavior. 9.93

analog-digital conversion speaking generally, it is important to note that almost any op amp or data converter input will break down, given sufficient overvoltage to the positive or negative rail. under breakdown conditions high and uncontrolled current can flow, so the danger is obvious. the exact breakdown voltage is entirely dependent on the individual op amp input stage. it may be a 0.6-v diode drop, or a process-related breakdown of 50 v or more. in many cases, overvoltage stress can result in currents over 100 ma, which destroys a part almost instantly. therefore, unless otherwise stated on the data sheet, input fault current should be limited to ≤5 ma to avoid damage. this is a conservative guideline, based on metal trace widths in a typical op amp or data converter input. higher levels of current can cause metal migration, a cumulative effect, which, if sustained, eventually leads to an open trace. should a migration situation be present, failure may only appear after a long time due to multiple overvoltages, a very difficult failure to identify. so, even though an amplifier may appear to withstand overvoltage currents well above 5 ma for a short time period, it is important to limit the current to 5 ma (or preferably less) for long term reliability. figure 9.75 illustrates an external, general-purpose op amp cm protection circuit. the basis of this scheme is the use of schottky diodes d1 and d2, plus an external current limiting resistor, rlimit. with appropriate selection of these parts, input protection for a great many op amps can be ensured. note that an op amp may also have internal protection diodes to the supplies (as shown) which conduct at about 0.6-v forward drop above or below the respective rails. in this case however, the external schottky diodes effectively parallel any internal diodes, so the internal units never reach their threshold. diverting fault currents externally eliminates potential stress, protecting the op amp. rlimit rlimit 1kω 1kω d1 d1 1n5711 1n5711 vin vin i limit i limit iin(max) iin(max) < 5ma < 5ma d2 d2 1n5711 1n5711 + + _ _ +vs +vs -vs -vs vout vout cf cf rfb rfb 1kω 1kω figure 9.75: a general-purpose op amp cm overvoltage protection network using schottky clamp diodes with current limit resistance 9.94

hardware design techniques 9.4 overvoltage protection the external diodes also allow other degrees of freedom, some not so obvious. for example, if fault current is allowed to flow in the op amp, rlimit must then be chosen so that the maximum current is no more than 5 ma for the worst case vin. this criterion can result in rather large rlimit values, and the associated increase in noise and offset voltage may not be acceptable. for instance, to protect against a vin of 100 v with the 5-ma criterion, rlimit must be ≥20 kω. however with external schottky clamping diodes, this allows rlimit to be governed by the maximum allowable d1-d2 current, which can be larger than 5 ma. however, care must be used here, for at very high currents the schottky diode drop may exceed 0.6 v, possibly activating internal op amp diodes. it is very useful to keep the rlimit value as low as possible, to minimize offset and noise errors. rlimit, in series with the op amp input, produces a bias-current-proportional voltage drop. left uncorrected, this voltage appears as an increase in the circuit's offset voltage. thus for op amps where the bias currents are moderate and approximately equal (most bipolar types) compensation resistor rfb balances the dc effect, and minimizes this error. for low bias current op amps (ib ≤10 na, or fet types) it is likely rfb won't be necessary. to minimize noise associated with rfb, bypass it with a capacitor, cf. clamping diode leakage for obvious reasons, it is critical that diodes used for protective clamping at an op amp input have a leakage sufficiently low to not interfere with the bias level of the application. figure 9.76 illustrates how some well-known diodes differ in terms of leakage current, as a function of the reverse bias voltage, vbias. r e v e r s e c u r r e n t 100na 100pa 100fa 100aa 1n5711 1n914 2n5457 jfet diode pn4117 jfet diode 150uv 1.0mv 10mv 100mv 1.0v 10v vbias figure 9.76: reverse bias current characteristics for diodes useful in protective clamping networks (pspice simulation) 9.95

analog-digital conversion in this chart, a 25°c simulation using pspice diode models, it is easy to see that not only is the diode type critical, so is the reverse bias. the 1n5711 schottky type for example, has a leakage of nearly 100 na at a reverse bias of 15 v, as it would typically be used with a ±15-v powered op amp. with this level of leakage, such diodes will only be useful with op amps with bias currents of several µa. for protection of appreciably lower bias current op amps (particularly most fet input devices) much lower leakage is necessary. as the data of figure 9.76 shows, not only does selecting a better diode help control leakage current, but operating it at a low bias voltage condition reduces leakage substantially. for example, while an ordinary 1n914 or 1n4148 diode may have 200-pa of leakage at 15 v, this is reduced to slightly more than 1 pa with bias controlled to 1 mv. but there is a caveat here! when used in a high impedance clamp circuit, glass diodes such as the 1n914/1n4148 families should either be shielded from incident light, or use opaque packages. this is necessary to minimize parasitic photocurrent from the surrounding light, which effectively appears as diode leakage current. specialty diodes with much lower leakage are also available, such as diode-connected fet devices characterized as protection diodes (see dpad series of reference 2). within the data of figure 9.76, the 2n5457 is a general purpose jfet, and the 2n4117/pn4117 family consists of parts designed for low current levels. other low leakage and specialty diodes are described in references 3 and 4. finally, whenever protective diodes are used, the effects of their capacitance on circuit performance must be analyzed. a flexible voltage follower protection circuit of course, it isn't a simple matter to effectively apply protective clamping to op amp inputs, while reducing diode bias level to a sub-mv level. the circuit of figure 9.77 shows low-leakage input clamping and other means used with a follower connected fet op amp, with protection at input and output, for both power on or off conditions. disregarding the various diodes momentarily, this circuit is an output-current-limited voltage follower. with the addition of diodes d1-d2 and d3-d4, it has both a voltage- limited output, and an overvoltage protected input. operating below the voltage threshold of output series-connected zener diodes d3-d4, the circuit behaves as a precision voltage follower. under normal follower operation, that is at input/output voltages < | vz + 0.6 | volts (where vz is the breakdown voltage of d3 or d4), diodes d1-d2 see only the combined offset and cm voltage errors of u1 as bias voltage. this reduces the d1-d2 leakage to very low levels, consistent with the pa level bias current of a fet input op amp. note that d1-d2 must be prevented from photo-conduction, and one direct means of this is to use opaque package diodes, such as the 2n3906 eb junctions discussed by pease (see references 3 and 4). if 1n914s are used they must be light shielded. in either case, bootstrapping greatly reduces the effective d1-d2 leakage. 9.96

hardware design techniques 9.4 overvoltage protection +vs 15v cf 10pf rf 10kω k1 close on power down vin rlimit 10kω vclamp u1 ad820 vclamp(+) ~ |vd3 + 1.2v| vclamp(-) ~ -|vd4 + 1.2v| d1 * * d1, d2 must be shielded from ambient light -- use to92 transistor eb junctions, i.e., 2n3906 d2 * -vs -15v rout1 100ω rout2 100ω vout d3 1n5240b 10v d4 1n5240b 10v figure 9.77: bootstrapping the d1-d2 protection network reduces diode leakage to negligible levels, and is voltage-programmable for clamp level for input/output voltage levels greater than vz + 0.6 v, zener diodes d3-d4 breakdown. this action clamps both the vout output node and the vclamp node via d1-d2. the input of the op amp is clamped to either polarity of the two input levels of vclamp, as indicated within the figure. under clamp conditions, input voltage vin can rise to levels beyond the supply rails of u1 without harm, with excess current limited by rlimit. if sustained high- level (~100 v) inputs will be applied, rlimit should be rated as a 1-2 w (or fusible) type. this circuit has very good dc characteristics, due to the fact that the clamping network is bootstrapped. this produces very low input/output errors below the vclamp threshold (consistent with the op amp specifications, of course). note that this bootstrapping has ac benefits as well, as it reduces the d1-d2 capacitance seen by the source. while the ~100-pf capacitance of d3-d4 might cause a loading problem with some op amps, this is mitigated by the isolating effect of rout1, plus the feedback compensation of cf. both rout1 and rout2 protect the op amp output. the input voltage clamping level is also programmable, and is set by the choice of zener voltage vz. this voltage plus 1.2 v should be greater than the maximum input, but below the rail voltage, as summarized in the figure. the example uses 10 v ± 5% zener diodes, so input clamping typically will occur at ±11.2 v, allowing ±10-v swings. an important caveat to the above is that it applies for power on conditions. with power off, d1-d4 still clamp to the noted levels, but this now produces a condition whereby the u1 input and output voltage can exceed the rails. note that this could be dangerous, for a given u1 device. if so, an optional and simple means towards providing a lower, safe clamping level for power off conditions is to use a 9.97

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analog-digital conversion relay at the vclamp node. the contacts are open with power applied, and closed with power absent. with attention paid to an overall pcb layout, this can preserve a pa level bias current of fet op amps used for u1. common-mode overvoltage protection using cmos channel protectors a much simpler alternative for overvoltage protection is the cmos channel protector. a channel protector is a device in series with the signal path, for example preceding an op amp input. it provides overvoltage protection by dynamically altering its resistance under fault conditions. functionally, it has the distinct advantage of affording protection for sensitive components from voltage transients, whether the power supplies are present or not. representative devices are the adg465/adg466/adg467, which are channel protectors with single, triple, and octal channel options. because this form of protection works whether supplies are present or not, the devices are ideal for use in applications where input overvoltages are common, or where correct power sequencing can’t always be guaranteed. one such example is within hot-insertion rack systems. an application of a channel protector for overvoltage protection of a precision buffer circuit is shown in figure 9.78. a single channel device, the adg465 at u2, is used here at the input of the u1 precision op amp buffer, an op777. vdd -1.5v vss +2v vd vdd u2 adg465 vs vin (rs <1kω) vd vs vss 15v cf 100pf rf 1kω u1 op777 -15v rout 100ω vout figure 9.78: using an adg465 channel protector ic with a precision buffer offers great simplicity of protection and fail-safe operation during power off a channel protector behaves just like a series resistor of 60 ω to 80 ω in normal operation (i.e., non-fault conditions). consisting of a series connection of multiple p and n mosfets, the protector dynamically adjusts channel resistance according to the voltage seen at the vd terminal. normal conduction occurs with vd more than a threshold level above or below the rails, i.e., (vss + 2 v) < vd < (vdd – 1.5 v). for fault conditions the analog input voltage exceeds this range, causing one of the series mosfets to switch off, thus raising the channel resistance to a high level. this clamps the vs output at one extreme range, either vss + 2 v or vdd – 1.5 v, as shown in figure 9.78. a major channel protector advantage is the fact that both circuit and signal source protection are provided, in the event of overvoltage or power loss. although shown here 9.98

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hardware design techniques 9.4 overvoltage protection operating from op amp ±15-v supplies, these channel protectors can handle total supplies of up to 40 v. they also can withstand overvoltage inputs from vss – 20 v to vdd + 20 v with power on (or ±35 v in the circuit shown). with power off (vdd = vss = 0 v), maximum input voltage is ±35 v. maximum room temperature channel leakage is 1 na, making them suitable for op amps and in-amps with bias currents of several na and up. related to the adg46x series of channel protectors are several fault-protected multiplexers, for example the adg508f/509f, and the adg438f/439f families. both the channel protectors and the fault-protected multiplexers are low power devices, and even under fault conditions, their supply current is limited to sub microampere levels. a further advantage of the fault-protected multiplexer devices is that they retain proper channel isolation, even for input conditions of one channel seeing an overvoltage, that is the remaining channels still function. cm overvoltage protection using high cm voltage in-amp the ultimate simplicity for analog channel overvoltage protection is achieved with resistive input attenuation ahead of a precision op amp. this combination equates to a high voltage capable in-amp, such as the ad629, which is able to linearly process differential signals riding upon cm voltages of up to ±270 v. further, and most important to overvoltage protection considerations, the on-chip resistors afford protection for either common mode or differential voltages of up to ±500 v. all of this is achieved by virtue of a precision laser-trimmed thin-film resistor array and op amp, as shown in figure 9.79. +vs 15v vin - + vout -vs -15v figure 9.79: the ad629 high voltage in-amp ic offers ± 500 v input overvoltage protection, one-component simplicity, and fail-safe power off operation examination of this topology shows that the resistive network around the ad629's precision op amp acts to divide down the applied cm voltage at vin by a factor of 20/1. the ad629 simultaneously processes the input differential mode signal vin to a single- ended output referred to a local ground, at a gain factor of unity. gain errors are no more 9.99

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analog-digital conversion than ±0.03 or 0.05%, while offset voltage is no more than 0.5 or 1 mv (grade dependent). the ad629 operates over a supply range of ±2.5 to ±18 v. these factors combine to make the ad629 a simple, one-component choice for the protection of off-card analog inputs that can potentially see dangerous transient voltages. due to the relatively high resistor values used, protection of the device is also inherent with no power applied, since the input resistors safely limit fault currents. in addition, it offers those operating advantages inherent to an in-amp: high cmr (86 db minimum at 500 hz), excellent overall dc precision, and the flexibility of simple polarity changes. on the flip side of performance issues, several factors make the ad629's output noise and drift relatively high, if compared to a lower gain in-amp configuration such as the amp03. these are the johnson noise of the high value resistors, and the high noise gain of the topology (21×). these factors raise the op amp noise and drift along with the resistor noise by a factor higher than typical. of course, whether or not this is an issue relevant to an individual application will require evaluation on a case-by-case basis. inverting mode op amp protection schemes there are some special cases of overvoltage protection requirements that don’t fit into the more general cm protection schemes above. figure 9.80 is one such example, a low bias current fet input op amp i/v converter. +vss 100v is rlimit 100kω d1 d2 d1, d2 pad1 (or dpad1) rf 1megω vout ad795 cf (trim) figure 9.80: a low bias current fet input op amp i/v converter with overvoltage protection network rlimit and d1 9.100

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hardware design techniques 9.4 overvoltage protection in this circuit the ad795 1-pa bias current op amp is used as a precision inverter. some current-source generated signals can originate from a high voltage potential, such as the 100-v vss level shown. as such, they have the potential of developing fault voltage levels beyond the op amp rails, producing fault current into the op amp well above safe levels. to prevent this, protection resistor rlimit is used inside the feedback loop as shown, along with voltage clamp d1 (d2). for normal signal condition (i.e., is ≤ 10 µa) the op amp's inverting node is very close to ground, with just a tiny voltage drop across rlimit. normal i/v conversion takes place, with gain set by rf. for protection, d1 is a special low leakage diode, clamping any excess voltage at the (–) node to ~0.6 v, thus protecting the op amp. the value of rlimit is chosen to allow a 1-ma max current under fault conditions. bootstrapping the d1 (and/or d2) clamp diodes as shown minimizes the normal operating voltage across the inverting node, keeping the diode leakage low (see figure 9.76, again). note that for a positive source voltage as shown, only positive clamping is needed, so just one diode suffices. only the lowest leakage diodes (≤1 pa) such as the pad1 (or the dpad1 dual) should be used in this circuit. as noted previously, any clamping diode used here should be shielded from light or use opaque packaging, to minimize photocurrent from ambient light. even so, the diode(s) will increase the net input current and shunt capacitance, and feedback compensation cf will likely be necessary to control response peaking. cf should be a very low leakage type. also, with the use of very low input bias current devices such as the ad795, it isn't possible to use the same level of internal protection circuitry as with other adi op amps. this factor makes the ad795 more sensitive to handling, so esd precautions should be taken. amplifier output voltage phase-reversal as alluded to above, there are "gray-area" op amp groups that have anomalous cm voltage zones, falling between the supply rails. as such, protection for these devices cannot be guaranteed by simply ensuring that the inputs stay between the rails—they must additionally stay entirely within their rated cm range, for consistent behavior. peculiar to some op amps, this misbehavior phenomenon is called output voltage phase- reversal. it is seen when one or both of the op amp inputs exceeds their allowable input cm voltage range. note that the inputs may still be well within the extremes of rail voltage, but simply below one specified cm limit. typically, this is towards the negative range. phase-reversal is most often associated with jfet and/or bifet amplifiers, but some bipolar single-supply amplifiers are also susceptible to it. the figure 9.81 waveforms illustrates this general phenomenon, with an overdriven voltage follower input on the left, and the resulting output phase-reversal at the right. while the specific details of the internal mechanism may vary with individual op amps, it suffices to say that the output phase-reversal occurs when a critical section of the amplifier front end saturates, causing the input-output sign relationship to temporarily reverse. under this condition, when the cm range is exceeded, the negative going input 9.101

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analog-digital conversion waveform in figure 9.81 (left) does not continue going more negative in the output waveform, figure 9.81 (right). instead, the input-output relationship phase-reverses, with the output suddenly going positive, i.e., the spike. it is important to note that this is not a latching form of phase-reversal, as the output will once again continue to properly track the input, when the input returns to the cm range. in figure 9.81, this can be seen in the continuance of the output sine wave, after the positive-going phase-reversal spike settles. figure 9.81: an illustration of input overdriving waveform (left) and the resulting output phase-reversal (right), using a jfet input op amp in most applications, this output voltage phase-reversal does no harm to the op amp, nor to the circuit where it is used. indeed, since it is triggered when the cm limit is exceeded, non-inverting stages with appreciable signal gain never see it, since their applied cm voltage is too small. note that with inverting applications the output phase-reversal problem is non-existent, as the cm range isn't exercised. so, although a number of (mostly older) op amps suffer from phase-reversal, it still is rarely a serious problem in system design. nevertheless, when and if a phase-reversal susceptible amplifier used in a servo loop application sees excess cm voltage, the effect can be disastrous—it goes bang! so, the best advice is to be forewarned. an output phase-reversal do-it-yourself test since output phase-reversal may not always be fully described on a data sheet, it is quite useful to test for it. this is easily done in the lab, by driving a questionable op amp as a unity-gain follower, from a source impedance (rlimit) of ~1 kω. it is helpful to make this a variable, 1 to 100-kω range resistance. with a low resistance setting (1 kω), while bringing the driving signal level slowly up towards the rail limits, observe the amplifier output. if a phase-reversal mechanism is present, when the cm limit of the op amp is exceeded, the output will suddenly reverse (see figure 9.81, again). if there is no phase-reversal present in an amplifier, the output waveform will simply clip at the limits of its swing. it may prove helpful to have a well- 9.102

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hardware design techniques 9.4 overvoltage protection behaved op amp available for this test, to serve as a performance reference. one such device is the ad8610. note that in general, some care should be used with this test. without a series current- limit resistor, if the generator impedance is too low (or level too high), it could possibly damage an internal junction of the op amp under test. so, obviously, caution is best for such cases. once a suitable rlimit resistance value is found, well-behaved op amps will simply show a smooth, bipolar range, clipped output waveform when overdriven. this clipping will appear more like the upper (positive swing) portion of the waveform within fig. 9.81, right (again). fixes for output phase–reversal an op amp manufacturer might not always give the rlimit resistance value appropriate to prevent output phase-reversal. but, the value can be determined empirically with the driving method mentioned above. most often, the rlimit resistor value providing protection against phase-reversal will also safely limit fault current through any input cm clamping diodes. if in doubt, a nominal value of 1 kω is a good starting point for testing. typically, fet input op amps will need only the current limiting series resistor for protection, but bipolar input devices are best protected with this same limiting resistor, along with a schottky diode (i.e., rlimit and d2, of figure 9.75, again). for a more detailed description of the output voltage phase-reversal effect, see references 7 and 8. figure 9.82 summarizes a number of the key points relating to output voltage phase-reversal. (cid:139) non-latching inversion of transfer function, triggered by exceeding common mode limit (cid:139) sometimes occurs in fet and bipolar (single-supply) op amps (cid:139) doesn’t harm amplifier… but disastrous for servo systems! (cid:139) not usually specified on data sheet, so amplifier must be checked (cid:139) easily prevented: (cid:122) all op amps: limit applied cm voltage by clamping or other means (cid:122) bifets: add series input resistance, rlimit (cid:122) bipolars: rlimit and schottky clamp diode to rail figure 9.82: a summary of key points regarding output phase-reversal in fet and bipolar input op amps 9.103

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analog-digital conversion alternately, any of the several previously mentioned cm clamping schemes can be used to prevent output phase-reversal, by setting the clamp voltage to be less than the amplifier cm range limit where phase-reversal occurs. for example, figure 9.77 would operate to prevent phase-reversal in fet amplifiers susceptible to it, if the negative clamp limit is set so that vclamp(–) never exceeds the typical negative cm range of –11 v on a –15-v rail. for validation of this or any of the previous overvoltage protection schemes, the circuit should be verified on a number of op amps, over a range of conditions as suitable to the final application environment. input differential protection the discussions thus far have been on overvoltage common-mode conditions, which is typically associated with forward biasing of pn junctions inherent in the structure of the input stage. there is another equally important aspect of protection against overvoltage, which is that due to excess differential voltages. excessive differential voltage, when applied to certain op amps, can lead to degradation of their operating characteristics. this degradation is brought about by reverse junction breakdown, a second case of undesirable input stage conduction, occurring under conditions of differential overvoltage. however, in the case of reverse breakdown of a pn junction, the problem can be more subtle in nature. it is illustrated by the partial op amp input stage in figure 9.83 q1a q1b q2b q2a d1 d2 inputs figure 9.83: an op amp input stage with d1-d2 input differential overvoltage protection network this circuit, applicable to a low noise op amp such as the op27, is also typical of many others using low noise bipolar transistors for differential pair q1-q2. in the absence of any protection, it can be shown that voltages above about 7 v between the two inputs will cause a reverse junction breakdown of either q2 or q1 (dependent upon relative polarity). note that, in cases of emitter-base breakdown, even small reverse currents can cause degradation in both transistor gain and noise (see reference 6). after emitter-base breakdown occurs, op amp parameters such as the bias currents and noise may well be out of specification. this is usually permanent, and it can occur gradually and quite 9.104

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hardware design techniques 9.4 overvoltage protection subtly, particularly if triggered by transients. for these reasons, virtually all low-noise op amps, whether npn or pnp based, utilize protection diodes such as d1-d2 across the inputs. these diodes conduct for applied voltages greater than ±0.6 v, protecting the transistors. the dotted series resistors function as current limiters (protection for the protection diodes) but aren’t used in all cases. for example, the ad797 doesn't have the resistors, simply because they would degrade the part's specified noise of 1 nv/√hz. note—when the resistors are absent internally, some means of external current limiting must be provided, when and if differential overvoltage conditions do occur. obviously, this is a tradeoff situation, so the confidence of full protection must be weighed against the noise degradation. note that an application circuit itself may provide sufficient resistance in the op amp inputs, such that additional resistance isn't needed. in applying a low noise bipolar input stage op amp, first check the chosen part's data sheet for internal protection. when necessary, protection diodes d1-d2, if not internal to the op amp, should be added to guarantee prevention of q1-q2 emitter-base breakdown. if differential transients of more than 5 v can be seen by the op amp in the application, the diodes are in order. ordinary low capacitance diodes will suffice, such as the 1n4148 family. add current limiting resistors as necessary, to limit diode current to safe levels. other ic device junctions, such as base-collector and jfet gate-source junctions don't exhibit the same degradation in performance upon break down, and for these the input current should be limited to 5 ma, unless the data sheet specifies a different value. protecting in-amps against overvoltage from a protection standpoint, instrumentation amplifiers (in-amps) are similar in many ways to op amps. like op amps, their absolute maximum ratings must be observed for both common and differential mode input voltages. a much simplified schematic of the ad620 in-amp is shown in figure 9.84, showing the input differential transistors and their associated protection parts. an important point, unique to the ad620 device, is the fact that the 400-ω internal rs protection resistors are thin-film types. therefore these resistors don't show symptoms of diode-like conduction to the ic substrate (as would be the case were they diffused resistors). practically, this means that the input ends of these resistors (pins 3 and 2) can go above or below the supplies. differential fault currents will be limited by the combination of twice the internal rs plus the external gain resistance, rg. excess applied cm voltages will show current limited by rs. in more detail, it can be noted that input transistors q1 and q2 have protection diodes d1 and d2 across their base-emitter junctions, to prevent reverse breakdown. for differential voltages, analysis shows that a fault current, iin, flows through the external rlimit resistors (if present), the internal rs resistors, the gain-setting resistor rg, and two diode drops (q2, d1). for the ad620 topology, rg varies inversely with gain, and a worst case (lowest resistance) occurs with the maximum gain of 1000, when rg is 49.9 ω. therefore the lowest total internal path series resistance is about 850 ω. 9.105

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analog-digital conversion r lim it (+) 3 vin 2 rl im it(-) r s 400ω ad620 iin r s 400ω d2 8 1 r g d1 q2 q1 figure 9.84: the ad620 in-amp input internally uses d1-d2 and series resistors rs for protection (additional protection can be added externally) for the ad620, any combination of cm and differential input voltages should be limited to levels that limit the input fault current to 20 ma, maximum. a purely differential voltage of 17 v would result in this current level, for the lowest resistance case. for cm voltages which may go beyond either rail, an internal diode not shown in fig. 9.84 conducts, effectively clamping the driven input to either +vs or –vs at the rs inner end. for this overvoltage cm condition, the 400-ω value of rs and the excess voltage beyond the rail determines the current level. if for example vin is 23 v with +vs at 15 v, 8 v appears across rs, and the 20-ma current rating is reached. higher fault voltages can be dealt with by adding rlimit resistance, to maintain fault current at 20 ma or less. a more generalized external voltage protection circuit for an in-amp like the ad620 is shown in figure 9.85. in this circuit, low-leakage diodes d3-d6 are used as cm clamps. since the in-amp bias current may be only 1 na or so (for the ad620), a low-leakage diode type is mandatory. as can be noted from the topology, diode bootstrapping isn’t possible with this configuration. it should be noted that not only must the diodes have basically low leakage, they must also maintain low leakage at the highest expected temperature. this suggests either fet type diodes (see fig. 9.76, again), or the transistor c-b types shown. the rlimit resistors are chosen to limit the maximum diode current under fault conditions. if additional differential protection is used, either back-back zener or transzorb clamps can be used, shown as d1-d2. if this is done, the leakage and capacitance of these diodes should be carefully considered. 9.106

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analog-digital conversion because the nature of a channel protection device is to turn off as vin approaches either rail, the scheme of figure 9.86 doesn't function with rail sensing single-supply in-amps. if near-rail operation and protection is required in an in-amp application, an alternative method is necessary. many single-supply in-amps are topologically similar to the two- amplifier in-amp circuit which is shown within the dotted box of figure 9.87. +vs +vs rlimit rlimit rlimit rlimit vout vout + + _ _ a2 a2 r1' r1' v2 v2 r2' r2' g = g = 1 + 1 + r2 r2 r1 + r1 + 2r2 2r2 rg rg + + _ _ a1 a1 r1 r1 r2 r2 vref vref rg rg figure 9.87: single-supply in-amps may or may not require external protection in the form of resistors and clamp diodes— if so, they can be added as shown in terms of the necessity for externally added protection components, a given in-amp may or may not require them. each case needs to be considered individually. for example, some in-amps have clamp diodes as shown, but internal to the device. the ad623 is such a part, but it lacks the series resistors, which can be added externally when and if necessary. note that this approach allows the rlimit value to be optimized for protection, with negligible impact on noise for those applications not needing the protection. also, some in-amp devices have both internal protection resistors and clamping diodes, an example here is the ad627. in this device, the internal protection is adequate for transients up to 40 v beyond the supplies (a 20-ma fault current in the internal resistors). for overvoltage levels higher than this, external rlimit resistors can be added. the use of the schottky diodes as shown at the two inputs is an option for in-amp protection. if no clamping is specifically provided internally, then they are applicable. their use is generally similar to the op amp protection case of figure 9.75, with comparable caveats as far as leakage. note that in many cases, due to internal protection networks of modern in-amps, these diodes just won’t be necessary. but again, there aren’t hard rules on this, so always check the data sheet before finalizing an application. adcs whose input range falls between the supply rails can generally be protected with external schottky diodes and a current limit resistor as shown in figure 9.88. even if 9.108

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analog-digital conversion overvoltage protection using cmos channel protectors the adg465/adg466/adg467 are cmos channel protectors which are placed in series with the signal path. the channel protector will protect sensitive components from voltage transients whether the power supplies are present or not. because the channel protection works whether the supplies are present or not, the channel protectors are ideal for use in applications where correct power sequencing cannot always be guaranteed (e.g., hot-insertion rack systems) to protect analog inputs. each channel protector (see figure 9.90) has an independent operation and consists of four mos transistors—two nmos and two pmos. one of the pmos devices does not lie directly in the signal path but is used to connect the source of the second pmos device to its backgate. this has the effect of lowering the threshold voltage and so increasing the input signal range of the channel for normal operation. the source and backgate of the nmos devices are connected for the same reason. vdd vd vs vss vss pmos vdd – 1.5v vss + 2v nmos nmos vd vs pmos vdd vss vdd figure 9.90: adg465, adg466, and adg467 single, triple, and octal channel protectors the channel protector behaves just like a series resistor (60 ω to 80 ω) during normal operation, i.e., (vss + 2 v) < vd < (vdd – 1.5 v). when a channel's analog input voltage exceeds this range, one of the mosfets will switch off, clamping the output at either vss + 2 v or vdd – 1.5 v. circuitry and signal source protection is provided in the event of an overvoltage or power loss. the channel protectors can withstand overvoltage inputs from vss – 20 v to vdd + 20 v with power on (vdd – vss = 44 v maximum). with power off (vdd = vss = 0 v), maximum input voltage is ±35 v. the channel protectors are very low power devices, and even under fault conditions, the supply current is limited to sub microampere levels. all transistors are dielectrically 9.110

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hardware design techniques 9.4 overvoltage protection isolated from each other using a trench isolation method thereby ensuring that the channel protectors cannot latch up. figure 9.91 shows a typical application that requires overvoltage and power supply sequencing protection. the application shows a hot-insertion rack system. this involves plugging a circuit board or module into a live rack via an edge connector. in this type of application it is not possible to guarantee correct power supply sequencing. correct power supply sequencing means that the power supplies should be connected before any external signals. incorrect power sequencing can cause a cmos device to latch up. this is true of most cmos devices regardless of the functionality. rc networks are used on the supplies of the channel protector to ensure that the rest of the circuit is powered up before the channel protectors. in this way, the outputs of the channel protectors are clamped well below vdd and vss until the capacitors are charged. the diodes ensure that the supplies on the channel protector never exceed the supply rails when it is being disconnected. again this ensures that signals on the inputs of the cmos devices never exceed the supplies. edge connector +5v –5v vdd vss analog in –2.5v to +2.5v logic logic gnd adc control logic adg466 figure 9.91: overvoltage and power supply sequencing protection using the adg466 digital isolators one way to break ground loops is to use digital isolation techniques. analog isolation amplifiers find many applications where a high degree of isolation is required, such as in medical instrumentation. digital isolation techniques offer a reliable method of transmitting digital signals over interfaces with high common-mode voltages without introducing ground noise. 9.111

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analog-digital conversion optocouplers (also called optoisolators) are useful and available in a wide variety of styles and packages. a typical optocoupler based on an led and a phototransitor is shown in figure 9.92. a current of approximately 10 ma is applied to an led transmitter, and the light output is received by a phototransistor. the light produced by the led is sufficient to saturate the phototransistor. isolation of 5000 v rms to 7000 v rms is common. although excellent for digital signals, optocouplers are too nonlinear for most analog applications. one should also realize that since the phototransistor is operated in a saturated mode, rise and fall-times can range from 10 µs to 20 µs in slower devices, thereby limiting applications at high speeds. vdd1 (5v) 425ω 10kω vdd2 (5v) cmos gate iin vin iout vout gnd1 high voltage isolation barrier gnd2 (cid:139) uses light for transmission over a high voltage barrier (cid:139) the led is the transmitter, and the phototransistor is the receiver (cid:139) high voltage isolation: 5000v to 7000v rms (cid:139) non-linear -- best for digital or frequency information (cid:139) rise and fall-times can be 10 to 20µs in slower devices (cid:139) example: siemens ilq-1 quad (http://www.siemens.com) figure 9.92: digital isolation using led / phototransistor optocouplers a faster optocoupler architecture is shown in figure 9.93 and is based on an led and a photodiode. the led is again driven with a current of approximately 10 ma. this produces a light output sufficient to generate enough current in the receiving photodiode to develop a valid high logic level at the output of the transimpedance amplifier. speed can vary widely between optocouplers, and the fastest ones have propagation delays of 20 ns typical, and 40 ns maximum, and can handle data rates up to 25 mbps for nrz data. this corresponds to a maximum square wave operating frequency of 12.5 mhz, and a minimum allowable passable pulse width of 40 ns. the adum1100a and adum1100b are digital isolators based on analog devices' icoupler® technology. combining high speed cmos and monolithic air core transformer technology, these isolation components provide outstanding performance characteristics superior to the traditional optocouplers previously described. configured as pin-compatible replacements for existing high speed optocouplers, the adum1100a and adum1100b support data rates as high as 25 mbps and 100 mbps, respectively. a functional diagram of the devices is shown in figure 9.94. 9.112

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analog-digital conversion both the adum1100a and adum1100b operate at either 3.3-v or 5-v supply voltages, have propagation delays < 18 ns, edge asymmetry of <2 ns, and rise and fall-times <3 ns. they operate at very low power, less than 900 µa of quiescent current (sum of both sides) and a dynamic current of less than 160 µa per mbps of data rate. unlike common transformer implementations, the parts provide dc correctness with a patented refresh feature which continuously updates the output signal. the adum1300/adum1301 digital isolators offer 3 channels of isolation, and the adum1400/adum1401 isolators offer 4 channels of isolation. these devices operate from +2.7 v to + 5.5 v and have independent input and output power inputs allowing them to operate not only as isolators but also as logic level translators. the ad260/ad261 family of digital isolators isolates five digital control signals to/from high speed dsps, microcontrollers, or microprocessors. the ad260 also has a 1.5-w transformer for a 3.5-kv rms isolated external dc/dc power supply circuit. each line of the ad260 can handle digital signals up to 20 mhz (40 mbps) with a propagation delay of only 14 ns which allows for extremely fast data transmission. output waveform symmetry is maintained to within ±1 ns of the input so the ad260 can be used to accurately isolate time-based pulse width modulator (pwm) signals. a simplified schematic of one channel of the ad260/ad261 is shown in figure 9.95. the data input is passed through a schmitt trigger circuit, through a latch, and a special transmitter circuit which differentiates the edges of the digital input signal and drives the primary winding of a proprietary transformer with a "set-high/set-low" signal. the secondary of the isolation transformer drives a receiver with the same "set-hi/set-low" data which regenerates the original logic waveform. an internal circuit operates in the background which interrogates all inputs about every 5 µs and in the absence of logic transitions, sends appropriate "set-hi/set-low" data across the interface. recovery time from a fault condition or at power-up is thus between 5 µs and 10 µs. the power transformer (available on the ad260) is designed to operate between 150 khz and 250 khz and will easily deliver more than 1 w of isolated power when driven push- pull (5 v) on the transmitter side. different transformer taps, rectifier and regulator schemes will provide combinations of ±5 v, 15 v, 24 v, or even 30 v or higher. the output voltage when driven with a low voltage-drop drive will be 37 v p-p across the entire secondary with a 5-v push-pull drive. key specifications for the parts are given in figure 9.96. to summarize, figure 9.97 reviews the major points of the in-circuit overvoltage issues discussed in this section. 9.114

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analog-digital conversion (cid:139) input voltages must not exceed absolute maximum ratings (usually specified with respect to supply voltages) (cid:139) requires vin(cm) stay within a range extending to ≤0.3v beyond rails (–vs–0.3v ≥ vin ≤ +vs+0.3v) (cid:139) ic input stage fault currents must be limited (< 5ma unless otherwise specified) (cid:139) avoid reverse-bias breakdown in input stage junctions! (cid:139) differential and common mode ratings often differ (cid:139) no two amplifiers are exactly the same (cid:139) watch out for output phase-reversal in jfet and ss bipolar op amps! (cid:139) some ics contain internal input protection (cid:122) diode voltage clamps, current limiting resistors (or both) (cid:122) absolute maximum ratings must still be observed figure 9.97: a summary of in-circuit overvoltage points if these varied overvoltage precautions for op amps and in-amps seem complex, yes indeed, they are! whenever op amp (or in-amp or data converter) inputs (and outputs) go outside equipment boundaries, dangerous or destructive things can happen to them. obviously, these potentially hazardous situations should be anticipated, for highest reliability. fortunately, most applications are contained entirely within the equipment, and usually see inputs and outputs to/from other ics on the same power system. therefore clamping and protection schemes typically aren't necessary for these cases. out-of-circuit overvoltage protection linear ics such as op amps, in-amps, and data converters must also be protected prior to the time that they are mounted to a printed circuit board. that is an out-of-circuit state. in such a condition, ics are completely at the mercy of their environment as to what stressful voltage surges they may see. most often the harmful voltage surges come from electrostatic discharge, or, as more commonly referenced, esd. this is a single, fast, high current transfer of electrostatic charge resulting from one of two conditions. these conditions are: 1) direct contact transfer between two objects at different potentials (sometimes called contact discharge) 2) a high electrostatic field between two objects when they are in close proximity (sometimes called air discharge) the prime sources of static electricity are mostly insulators and are typically synthetic materials, e.g., vinyl or plastic work surfaces, insulated shoes, finished wood chairs, scotch tape, bubble pack, soldering irons with ungrounded tips, etc. voltage levels generated by these sources can be extremely high since their charge is not readily 9.116

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hardware design techniques 9.4 overvoltage protection distributed over their surfaces or conducted to other objects. the generation of static electricity caused by rubbing two substances together is called the triboelectric effect. some common examples of ordinary acts producing significant esd voltages are shown in figure 9.98. (cid:139) walking across a carpet 1000v - 1500v (cid:139) walking across a vinyl floor 150v - 250v (cid:139) handling material protected by clear plastic covers 400v - 600v (cid:139) handling polyethylene bags 1000v - 2000v (cid:139) pouring polyurethane foam into a box 1200v - 1500v (cid:139) note: above assumes 60% rh. for low rh (30%), voltages can be > 10 times figure 9.98: esd voltages generated by various ordinary circumstances ics can be damaged by the high voltages and high peak currents generated by esd. precision analog circuits, often featuring very low bias currents, are more susceptible to damage than common digital circuits, because traditional input-protection structures which protect against esd damage increase input leakage—and thus can't be used. for the design engineer or technician, the most common manifestation of esd damage is a catastrophic failure of the ic. however, exposure to esd can also cause increased leakage or degrade other parameters. if a device appears to not meet a data sheet specification during evaluation, the possibility of esd damage should be considered. figure 9.99 outlines some relevant points on esd induced failures. all esd-sensitive devices are shipped in protective packaging. ics are usually contained in either conductive foam or antistatic shipping tubes, and the container is then sealed in a static-dissipative plastic bag. the sealed bag is marked with a distinctive sticker, such as in figure 9.100, which outlines the appropriate handling procedures. the presence of outside package notices such as those shown in figure 9.100 is notice to the user that device handling procedures appropriate for esd protection are necessary. in addition, data sheets for esd-sensitive ics generally have a bold statement to that effect, as shown in figure 9.101. 9.117

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hardware design techniques 9.4 overvoltage protection warning! caution esd sensitive device esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adxxx features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. figure 9.101: esd data sheet statement for linear ics once esd-sensitive devices are identified, protection is relatively easy. obviously, keeping ics in their original protective packages as long as possible is a first step. a second step is discharging potentially damaging esd sources before ic damage occurs. discharging such voltages can be done quickly and safely, through a high impedance. a key component required for esd-safe ic handling is a workbench with a static- dissipative surface, shown in the workstation of figure 9.102. the surface is connected to ground through a 1-mω resistor, which dissipates any static charge, while protecting the user from electrical ground fault shock hazards. if existing bench tops are nonconductive, a static-dissipative mat should be added, along with the discharge resistor. personnel personnel ground strap ground strap esd protective esd protective trays, shunts, etc. trays, shunts, etc. esd protective esd protective table top table top esd esd protective protective floor or floor or mat mat building floor building floor note: conductive table top sheet resistance » 1mω note: conductive table top sheet resistance » 1mω figure 9.102: a workstation environment suitable for handling esd-sensitive ics 9.119

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analog-digital conversion note that the surface of the workbench has a moderately high sheet resistance. it is neither necessary nor desirable to use a low-resistance surface (such as a sheet of copper- clad pc board) for the work surface. remember, a high peak current may flow if a charged ic is discharged through a low impedance. this is precisely what happens when a charged ic contacts a grounded copper clad board. when the same charged ic is placed on the high impedance surface of figure 9.102 however, the peak current isn't high enough to damage the device. several personnel handling techniques are keys to minimizing esd-related damage. at the workstation, a conductive wrist strap is recommended while handling esd-sensitive devices. the wrist strap ensures that normal tasks, such as peeling tape from packages, won’t cause ic damage. again, a 1-mω resistor, from the wrist strap to ground, is required for safety. when building prototype breadboards or assembling pc boards which contain esd-sensitive ics, all passive components should be inserted and soldered before the ics. this minimizes the esd exposure of the sensitive devices. the soldering iron must, of course, have a grounded tip. protecting ics from esd requires the participation of both the ic manufacturer and the customer. ic manufacturers have a vested interest in providing the highest possible level of esd protection for their products. ic circuit designers, process engineers, packaging specialists and others are constantly looking for new and improved circuit designs, processes, and packaging methods to withstand or shunt esd energy. a complete esd protection plan, however, requires more than building esd protection into ics. the users of ics must also provide their employees with the necessary knowledge of and training in esd handling procedures, so that protection can be built in at all key points along the way, as outlined in figure 9.103. analog devices: analog devices: (cid:132) circuit design and fabrication - (cid:132) circuit design and fabrication - ↓ ↓ ↓ ↓ design and manufacture products with the highest level of esd design and manufacture products with the highest level of esd protection consistent with required analog and digital performance. protection consistent with required analog and digital performance. (cid:132) pack and ship - (cid:132) pack and ship - ↓ ↓ pack in static dissipative material. mark packages with esd warning. pack in static dissipative material. mark packages with esd warning. customers: customers: (cid:132) incoming inspection - (cid:132) incoming inspection - ↓ ↓ inspect at grounded workstation. minimize handling. inspect at grounded workstation. minimize handling. (cid:132) inventory control - (cid:132) inventory control - ↓ ↓ store in original esd-safe packaging. minimize handling. store in original esd-safe packaging. minimize handling. (cid:132) manufacturing - (cid:132) manufacturing - ↓ ↓ ↓ ↓ deliver to work area in original esd-safe packaging. open packages only at deliver to work area in original esd-safe packaging. open packages only at grounded workstation. package subassemblies in static dissipative packaging. grounded workstation. package subassemblies in static dissipative packaging. (cid:132) pack and ship - (cid:132) pack and ship - pack in static dissipative material if required. replacement or optional pack in static dissipative material if required. replacement or optional boards may require special attention. boards may require special attention. figure 9.103: esd protection requires a partner relationship between adi and the end customer with control at key points 9.120

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hardware design techniques 9.4 overvoltage protection special care should be taken when breadboarding and evaluating ics. the effects of esd damage can be cumulative, so repeated mishandling of a device can eventually cause a failure. inserting and removing ics from a test socket, storing devices during evaluation, and adding or removing external components on the breadboard should all be done while observing proper esd precautions. again, if a device fails during a prototype system development, repeated esd stress may be the cause. the key word to remember with respect to esd is prevention. there is no way to undo esd damage, or to compensate for its effects. esd models and testing some applications have higher sensitivity to esd than others. ics which are located on a pc board surrounded by other circuits are generally much less susceptible to esd damage than circuits which must interface with other pc boards or the outside world. these ics are generally not specified or guaranteed to meet any particular esd specification (with the exception of mil-std-883 method 3015 classified devices). a good example of an esd-sensitive interface is the rs-232 interface port ics on a computer, which can easily be exposed to excess voltages. in order to guarantee esd performance for such devices, the test methods and limits must be specified. a host of test waveforms and specifications have been developed to evaluate the susceptibility of devices to esd. the three most prominent of these waveforms currently in use for semiconductor or discrete devices are: the human body model (hbm), the machine model (mm), and the charged device model (cdm). each of these models represents a fundamentally different esd event, consequently, correlation between the test results for these models is minimal. since 1996, all electronic equipment sold to or within the european community must meet electromechanical compatibility (emc) levels as defined in specification iec1000-4-x. note that this does not apply to individual ics, but to the end equipment. these standards are defined along with test methods in the various iec1000 specifications, and are listed in figure 9.104. iec1000-4-2 specifies compliance testing using two coupling methods, contact discharge and air-gap discharge. contact discharge calls for a direct connection to the unit being tested. air-gap discharge uses a higher test voltage, but does not make direct contact with the unit under test. with air discharge, the discharge gun is moved toward the unit under test, developing an arc across the air gap, hence the term air discharge. this method is influenced by humidity, temperature, barometric pressure, distance and rate of closure of the discharge gun. the contact-discharge method, while less realistic, is more repeatable and is gaining acceptance in preference to the air-gap method. 9.121

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analog-digital conversion (cid:139) iec1000-4 (cid:139) iec1000-4 electromagnetic compatibility emc electromagnetic compatibility emc (cid:139) iec1000-4-1 overview of immunity tests (cid:139) iec1000-4-1 overview of immunity tests (cid:139) iec1000-4-2 electrostatic discharge immunity (esd) (cid:139) iec1000-4-2 electrostatic discharge immunity (esd) (cid:139) iec1000-4-3 radiated radio-frequency electromagnetic field immunity (cid:139) iec1000-4-3 radiated radio-frequency electromagnetic field immunity (cid:139) iec1000-4-4 electrical fast transients (eft) (cid:139) iec1000-4-4 electrical fast transients (eft) (cid:139) iec1000-4-5 lightening surges (cid:139) iec1000-4-5 lightening surges (cid:139) iec1000-4-6 conducted radio frequency disturbances above 9khz (cid:139) iec1000-4-6 conducted radio frequency disturbances above 9khz (cid:139) compliance marking: (cid:139) compliance marking: figure 9.104: a listing of the iec standards applicable to esd specifications and testing procedures although very little energy is contained within an esd pulse, the extremely fast risetime coupled with high voltages can cause failures in unprotected ics. catastrophic destruction can occur immediately as a result of arcing or heating. even if catastrophic failure does not occur immediately, the device may suffer from parametric degradation, which may result in degraded performance. the cumulative effects of continuous exposure can eventually lead to complete failure. i-o lines are particularly vulnerable to esd damage. simply touching or plugging in an i-o cable can result in a static discharge that can damage or completely destroy the interface product connected to the i-o port (such as rs-232 line drivers and receivers). traditional esd test methods such as mil-std-883b method 3015.7 do not fully test a product's susceptibility to this type of discharge. this test was intended to test a product's susceptibility to esd damage during handling. each pin is tested with respect to all other pins. there are some important differences between the mil-std-883b method 3015.7 test and the iec test, noted as follows: 1) the iec test is much more stringent in terms of discharge energy. the peak current injected is over four times greater. 2) the current risetime is significantly faster in the iec test. 3) the iec test is carried out while power is applied to the device. it is possible that esd discharge could induce latch-up in the device under test. this test is therefore more representative of a real-world i-o discharge where the equipment is operating normally with power applied. for maximum confidence, however, both tests should be performed on interface devices, thus ensuring maximum protection both during handling, and later, during field service. 9.122

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hardware design techniques 9.4 overvoltage protection references: 9.4 overvoltage protection 1. walt kester, wes freeman, joe buxton, "overvoltage protection," portion of section 10 within walt kester, editor, practical design techniques for sensor signal conditioning, analog devices, inc., 1999, isbn 0-916550-20-6. 2. siliconix pad/jpad/sstpad series low leakage pico-amp diodes, vishay/siliconix, http://www.vishay.com/brands/siliconix/ssfsglld.html 3. bob pease, "bounding, clamping techniques improve circuit performance," edn, november 10, 1983, p. 277. 4. bob pease, "understanding diodes and their problems," chapter 6 within troubleshooting analog circuits, butterworth-heinemann, 1991, isbn 0-7506-9184-0. 5. dov kurz, avner cohen, "bootstrapping reduces amplifier input capacitance," edn, march 20, 1978. 6. c.d. motchenbacher, j.a. connelly, chapter 5, within low noise electronic system design, john wiley, 1993. 7. adolfo garcia, "operational amplifier output voltage phase reversal," section 11, pp. 1-10 within walt kester, editor, 1992 amplifier applications guide, analog devices, inc., norwood, ma, 1992, isbn 0-916550-10-9. 8. adolfo garcia, wes freeman, "overvoltage effects on analog integrated circuits," section 7 within walt kester, editor, practical analog design techniques, analog devices, inc., norwood, ma, 1995, isbn 0-916550-16-8. 9. charles kitchen, lew counts, a designer’s guide to instrumentation amplifiers, analog devices, inc., 2000. 10. walt kester, wes freeman, james bryant, "electrostatic discharge," portion of section 10 within walt kester, editor, practical design techniques for sensor signal conditioning, analog devices, inc., 1999, isbn 0-916550-20-6. 11. mil-std-883 method 3015, "electrostatic discharge sensitivity classification." available from standardization document order desk, 700 robbins ave., building #4, section d, philadelphia, pa, 19111-5094. 12. eiaj ed-4701 test method c-111, "electrostatic discharges." available from the japan electronics bureau, 250 w 34th st., new york ny 10119, attn.: tomoko. 13. esd association standard s5.2 for "electrostatic discharge (esd) sensitivity testing -machine model (mm)- component level." available from the esd association, inc., 200 liberty plaza, rome, ny 13440. 14. esd association draft standard ds5.3 for "electrostatic discharge (esd) sensitivity testing - charged device model (cdm) component testing." available from the esd association, inc., 200 liberty plaza, rome, ny 13440. 15. esd prevention manual, analog devices, inc. 16. niall lyne, "electrically induced damage to standard linear integrated circuits: the most common causes and the associated fixes to prevent reoccurrence," analog devices an397. 9.125

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hardware design techniques 9.5 thermal management section 9.5: thermal management walt jung for reliability reasons, data converter systems handling appreciable power are increasingly called upon to observe thermal management. all semiconductors have some specified safe upper limit for junction temperature (tj), usually on the order of 150°c (sometimes 175°c). like maximum power supply voltages, maximum junction temperature is a worst case limitation which must not be exceeded. in conservative designs, it won’t be approached by less than an ample safety margin. note that this is critical, since semiconductor lifetime is inversely related to operating junction temperature. simply put, the cooler ics are, the more they can approach their maximum life. this limitation of power and temperature is basic, and is illustrated by a typical data sheet statement as in figure 9.108. in this case it is for the ad8017ar, an 8-pin soic device. the maximum power that can be safely dissipated by the ad8017 is limited by the associated rise in junction temperature. the maximum safe junction temperature for plastic encapsulated device is determined by the glass transition temperature of the plastic, approximately +150°c. temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. exceeding a junction temperature of +175°c for an extended period can result in device failure. figure 9.108: maximum power dissipation data sheet statement for the ad8017ar, an adi thermally enhanced soic packaged device tied to these statements are certain conditions of operation, such as the power dissipated by the device, and the package mounting specifics to the printed circuit board (pcb). in the case of the ad8017ar, the part is rated for 1.3 w of power at an ambient of 25°c. this assumes operation of the 8-lead soic package on a two-layer pcb with about 4 in2 (~2500 mm2) of 2 oz. copper for heat sinking purposes. predicting safe operation for the device under other conditions is covered below. thermal basics the symbol θ is generally used to denote thermal resistance. thermal resistance is in units of °c/watt (°c/w). unless otherwise specified, it defines the resistance heat encounters transferring from a hot ic junction to the ambient air. it might also be expressed more specifically as θja, for thermal resistance, junction-to-ambient. θjc and θca are two additional θ forms used, and are further explained below. in general, a device with a thermal resistance θ equal to 100°c/w will exhibit a temperature differential of 100°c for a power dissipation of 1 w, as measured between two reference points. note that this is a linear relationship, so 1 w of dissipation in this part will produce a 100°c differential (and so on, for other powers). for the ad8017ar example, θ is about 95°c/w, so 1.3 w of dissipation produces about a 124°c junction-to- 9.127

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analog-digital conversion ambient temperature differential. it is of course this rise in temperature that is used to predict the internal temperature, in order to judge the thermal reliability of a design. with the ambient at 25°c, this allows an internal junction temperature of about 150°c. in practice most ambient temperatures are above 25°c, so less power can then be handled. for any power dissipation p (in watts), one can calculate the effective temperature differential (∆t) in °c as: ∆t = p × θ eq. 9.10 where θ is the total applicable thermal resistance. figure 9.109 summarizes a number of basic thermal relationships. (cid:139) θ = thermal resistance (°c/w) (cid:139) p = total device power dissipation (w) (cid:139) t = temperature (°c) (cid:139) ∆t = temperature differential = p × θ (cid:139) θja = junction-ambient thermal resistance (cid:139) θjc = junction-case thermal resistance (cid:139) θca = case-ambient thermal resistance (cid:139) θja = θjc + θca (cid:139) tj = ta + (p × θja) (cid:139) note: tj(max) = 150°c (sometimes 175°c) ta ambient θca tc case θjc tj junction figure 9.109: basic thermal relationships note that series thermal resistances, such as the two shown at the right, model the total thermal resistance path a device may see. therefore the total θ for calculation purposes is the sum, i.e., θja = θjc and θca. given the ambient temperature ta, p, and θ, then tj can be calculated. as the relationships signify, to maintain a low tj, either θ or the power being dissipated (or both) must be kept low. a low ∆t is the key to extending semiconductor lifetimes, as it leads to lower maximum junction temperatures. in ics, one temperature reference point is always the device junction, taken to mean the hottest spot inside the chip operating within a given package. the other relevant reference point will be either tc, the case of the device, or ta, that of the surrounding air. this then leads in turn to the above mentioned individual thermal resistances, θjc and θja. taking the most simple case first, θja is the thermal resistance of a given device measured between its junction and the ambient air. this thermal resistance is most often used with small, relatively low power ics such as op amps, which often dissipate 1 w or less. generally, θja figures typical of op amps and other small devices are on the order of 90-100°c/w for a plastic 8 pin dip package, as well as the better soic packages. 9.128

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hardware design techniques 9.5 thermal management it should be clearly understood that these thermal resistances are highly package dependent, as different materials have different degrees of thermal conductivity. as a general guideline, thermal resistance of conductors is analogous to electrical resistances, that is copper is the best, followed by aluminum, steel, and so on. thus copper lead frame packages offer the highest performance, i.e., the lowest θ. heat sinking by definition, a heat sink is an added low thermal resistance device attached to an ic to aid heat removal. a heat sink has additional thermal resistance of its own, θca, rated in °c/w. however, most current op amp packages don't easily lend themselves to heat sink attachment (exceptions are older to-99 metal can types). devices meant for heat sink attachment will often be noted by a θjc dramatically lower than the θja. in this case θ will be composed of more than one component. thermal impedances add, making a net calculation relatively simple. for example, to compute a net θja given a relevant θjc, the thermal resistance of the heat sink, θca, or case to ambient is added to the θjc as: θja = θjc + θca and the result is the θja for that specific circumstance. eq. 9.11 more generally however, modern ics don't use commercially available heat sinks. instead, when significant power needs to be dissipated, such as ≥1 w, low thermal resistance copper pcb traces are used as the heat sink. in such cases, the most useful form of manufacturer data for this heat sinking are the boundary conditions of a sample pcb layout, and the resulting θja for those conditions. this is in fact the type of specific information supplied for the ad8017ar, as mentioned earlier. applying this approach, example data illustrating thermal relationships for such conditions is shown by figure 9.110. these data apply for an ad8017ar mounted to a heat sink with an area of about 4 square inches on a 2 layer, 2 ounce copper pcb. figure 9.110: thermal rating curves for ad8017ar op amp 9.129

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analog-digital conversion these curves indicate the maximum power dissipation vs. temperature characteristic for the ad8017, for maximum junction temperatures of both 150°c and 125°c. such curves are often referred to as derating curves, since allowable power decreases with ambient temperature. with the ad8017ar, the proprietary adi thermal coastline ic package is used, which allows additional power to be dissipated with no increase in the so-8 package size. for a tj(max) of 150°c, the upper curve shows the allowable power in this package, which is 1.3 w at an ambient of 25°c. if a more conservative tj(max) of 125°c is used, the lower of the two curves applies. a performance comparison for an 8-pin standard soic and the adi thermal coastline version is shown in figure 9.111. note that the thermal coastline provides an allowable dissipation at 25°c of 1.3 w, whereas a standard package allows only 0.8 w. in the thermal coastline heat transferal is increased, accounting for the package's lower θja. ) ) w w ( ( i i i i i i n n o o t t a a p p s s s s d d r r e e w w o o p p m m u u m m x x a a m m i i 8-pin thermal coastline soic 8-pin thermal coastline soic 8-pin standard soic 8-pin standard soic 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 -50 -40 -30 -20 -10 -50 -40 -30 -20 -10 0 0 10 10 20 20 30 30 40 40 50 50 60 60 70 70 80 80 90 90 ambient temperature - (°c) ambient temperature - (°c) figure 9.111: thermal rating curves for standard (lower) and adi thermal coastline (upper) 8-pin soic packages even higher power dissipation is possible, with the use of ic packages better able to transfer heat from chip to pcb. an example is the ad8016 device, available with two package options rated for 5.5 and 3.5 w at 25°c, respectively, as shown in figure 9.112. taking the higher rated power option, the ad8016arp psop3 package, when used with a 10 inch2 1 oz. heat sink plane, the combination is able to handle up to 3 w of power at an ambient of 70°c, as noted by the upper curve. this corresponds to a θja of 18°c/w, which in this case applies for a maximum junction temperature of 125°c. 9.130

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analog-digital conversion both of the ad8016 package options are characterized for both still and moving air, but the thermal information given above applies without the use of directed airflow. therefore, adding additional airflow lowers thermal resistance further (see reference 2). for reliable, low thermal resistance designs with op amps, several design do's and don'ts are listed below. consider all of these points, as may be practical. 1) do use as large an area of copper as possible for a pcb heat sink, up to the point of diminishing returns. 2) in conjunction with 1), do use multiple (outside) pcb layers, connected together with multiple vias. 3) do use as heavy copper as is practical (2 oz. or more preferred). 4) do provide sufficient natural ventilation inlets and outlets within the system, to allow heat to freely move away from hot pcb surfaces. 5) do orient power-dissipating pcb planes vertically, for convection-aided airflow across heat sink areas. 6) do consider the use of external power buffer stages, for precision op amp applications. 7) do consider the use of forced air, for situations where several watts must be dissipated in a confined space. 8) don't use solder mask planes over heat dissipating traces. 9) don't use excessive supply voltages on ics delivering power. for the most part, these points are obvious. however, one that could use some elaboration is number 9. whenever an application requires only modest voltage swings (such as for example standard video, 2 v p-p) a wide supply voltage range can often be used. but, as the data of figure 9.114 indicates, operation of an op amp driver on higher supply voltages produces a large ic dissipation, even though the load power is constant. in such cases, as long as the distortion performance of the application doesn’t suffer, it can be advantageous to operate the ic on lower supplies, say ±5 v, as opposed to ±15 v. the above example data was calculated on a dc basis, which will generally tax the driver more in terms of power than a sine wave or a noise-like waveform, such as a dmt signal (see reference 2). the general principles still hold for these ac waveforms, i.e., the op amp power dissipation is high when load current is high and the voltage low. 9.132

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+2v +2v 150ω 150ω +vs +vs + + ad817 ad817 - - -vs -vs 1kω 1kω 1kω 1kω 400 400 power power (mw) (mw) +1v +1v 300 300 200 200 100 100 0 0 hardware design techniques 9.5 thermal management ps + pq = total ps + pq = total op amp power op amp power pq = quiescient power pq = quiescient power ps = signal power ps = signal power pr = load power pr = load power 0 0 5 5 10 10 15 15 ±vs, volts ±vs, volts figure 9.114: power dissipated in video op amp driver for various supply voltages with low voltage output swing while there is ample opportunity for high power handling with the thermally enhanced packages described above for the ad8016 and ad8017, the increasingly popular smaller ic packages actually move in an opposite direction. without question, it is true that today’s smaller packages do noticeably sacrifice thermal performance. but, it must be understood that this is done in the interest of realizing a smaller size for the packaged op amp, and, ultimately, a much greater final pcb density for the overall system. these points are illustrated by the thermal ratings for the ad8057 and ad8058 family of single and dual op amp devices, as is shown in figure 9.115. the ad8057 and ad8058 op amps are available in three different packages. these are the sot-23-5, and the 8-pin µsoic, along with standard soic. as the data shows, as the package size becomes smaller and smaller, much less power is capable of being removed. since the lead frame is the only heatsinking possible with such tiny packages, their thermal performance is thus reduced. the θja for the packages mentioned is 240, 200, and 160°c/w, respectively. note this is more of a package than device limitation. other ics with the same packages have similar characteristics. 9.133

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analog-digital conversion figure 9.115: comparative thermal performance for several ad8057/58 op amp package options data converter thermal considerations at first glance, one might assume that the power dissipation of an adc or a dac will remain constant for a given power supply voltage. however, many data converters, especially cmos ones, have power dissipations that are highly dependent upon not only output data loading but also the sampling clock frequency. since many of the newer high- speed converters can dissipate between 1.5 and 2 w maximum power under the worst case operating conditions, this point must be well understood in order to ensure that the package is mounted in such a way as to maintain the junction temperature within acceptable limits at the highest expected operating temperature. the previous discussion in this chapter on grounding emphasized that the digital outputs of high performance adcs, especially those with parallel outputs, should be lightly loaded (5-10 pf) in order to prevent digital transient currents from corrupting the snr and sfdr. even under light output loading, however, most cmos and bicmos adcs have power dissipations which are a function of sampling clock frequency and in some cases, the analog input frequency and amplitude. for example, figure 9.116 shows the ad9245 14-bit, 80-msps, 3-v cmos adc power dissipation versus frequency for a 2.5-mhz analog input and 5-pf output loading of the data lines. the graphs show the digital and analog power supply currents separately as well as the total power dissipation. note that total power dissipation can vary between approximately 310 mw and 380 mw as the sampling frequency is varied between 10 and 80 msps. 9.134

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analog-digital conversion it is recommended that the exposed center heatsink be soldered to the pc board ground plane to reduce the package θja to 23°c/w in still air. for 1.75 w of power dissipation, this places the junction temperature 23°c × 1.75 = 40.3°c above the ambient temperature. for a maximum operating temperature of +85°c, this places the junction at 85°c + 40.3°c = 125.3°c. the thermal resistance of the package can be reduced to 17°c/w with 200 lfpm airflow, thereby reducing the junction temperature to 30°c above the ambient, or 115°c for an operating ambient temperature of +85°c. high speed cmos dacs (such as the txdac® series) and dds ics (such as the ad985x series) also have clock-rate dependent power dissipation. for example, in the case of the ad9777 16-bit, 160-msps dual interpolating dac, power dissipation is a function of clock rate, output frequency, and the enabling of the pll and the modulation functions. power dissipation on 3.3-v supplies can range from 380 mw (fdac = 100 msps, fout = 1 mhz, no interpolation, no modulation) to 1.75 w (fdac = 400 msps, fdata = 50 mhz, fs/2 modulation, pll enabled). these and similar parts in the family are also offered in thermally enhanced packages with exposed pads for soldering to the pc board ground plane. these discussions on the thermal application issues of op amps and data converters haven't dealt with the classic techniques of using clip-on (or bolt-on) type heat sinks. they also have not addressed the use of forced air cooling, generally considered only when tens of watts must be handled. these omissions are mainly because these approaches are seldom possible or practical with today's op amp and data converter packages. the more general discussions within references 4-7 can be consulted for this and other supplementary information. 9.138

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hardware design techniques 9.6 emi/rfi considerations section 9.6: emi/rfi considerations james bryant, walt jung, walt kester analog circuit performance is often affected adversely by high frequency signals from nearby electrical activity. and, equipment containing your analog circuitry may also adversely affect systems external to it. reference 1 (page 4) describes this complementary transmission of undesirable high frequency signals from or into local equipment as per an iec50 definition. these corresponding aspects of the broad arena of electromagnetic compatibility, better known as emc, are: (cid:139) it describes the ability of electrical and electronic systems to operate without interfering with other systems… (cid:139) it also describes the ability of such systems to operate as intended within a specified electromagnetic environment. so, complete emc assurance would indicate that the equipment under design should neither produce spurious signals, nor should it be vulnerable to out-of-band external signals (i.e., those outside its intended frequency range). it is the latter class of emc problem to which analog equipment most often falls prey. and, it is the graceful handling of these spurious signals that are emphasized within this section. the externally produced electrical activity may generate noise, and is referred to either as electromagnetic interference (emi), or radio frequency interference (rfi). in this section, we will refer to emi in terms of both electromagnetic and radio frequency interference. one of the more challenging tasks of the analog designer is the control of equipment against undesired operation due to emi. it is important to note that in this context, emi and or rfi is almost always detrimental. once given entrance into your equipment, it can and will degrade its operation, quite often considerably. this section is oriented heavily towards minimizing undesirable analog circuit operation due to the receipt of emi/rfi. misbehavior of this sort is also known as emi or rfi susceptibility, indicating a tendency towards anomalous equipment behavior when exposed to emi/rfi. there is of course a complementary emc issue, namely with regard to spurious emissions. however, since analog circuits typically involve fewer pulsed, high speed, high current signal edges that give rise to such spurious signals (compared to high speed logic, for example), this aspect of emc isn't as heavily treated here. nevertheless, the reader should bear in mind that it can be important, particularly if the analog circuitry is part of a mixed-signal environment along with high speed logic. since all of these various emc design points can be critical, the end-of-chapter references are strongly recommended for supplementary study. indeed, for a thorough, fully competent design with respect to emi, rfi and emc, the designer will need to become intimately acquainted with one or more of these references (see references 1- 6). as for the material following, it is best viewed as an introduction to this extremely broad but increasingly important topic. 9.141

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analog-digital conversion emi/rfi mechanisms to understand and properly control emi and rfi, it is helpful to first segregate it into manageable portions. thus it is useful to remember that when emi/rfi problems do occur, they can be fundamentally broken down into a source, a path, and a receiver. as a systems designer, you have under your direct control the receiver part of this landscape, and perhaps some portion of the path. but seldom will the designer have control over the actual source. emi noise sources there are countless ways in which undesired noise can couple into an analog circuit to ruin its accuracy. some of the many examples of these noise sources are listed in figure 9.121. (cid:139) emi/rfi noise sources can couple from anywhere (cid:139) some common sources of externally generated noise: (cid:122) radio and tv broadcasts (cid:122) mobile radio communications (cid:122) cellular telephones (cid:122) vehicular ignition (cid:122) lightning (cid:122) utility power lines (cid:122) electric motors (cid:122) computers (cid:122) garage door openers (cid:122) telemetry equipment figure 9.121: some common emi noise sources since little control is possible over these sources of emi, the next best management tool one can exercise over them is to recognize and understand the possible paths by which they couple into the equipment under design. emi coupling paths the emi coupling paths are actually very few in terms of basic number. three very general paths are by: 1. interference due to conduction (common-impedance) 2. interference due to capacitive or inductive coupling (near-field interference) 3. electromagnetic radiation (far-field interference) 9.142

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hardware design techniques 9.6 emi/rfi considerations noise coupling mechanisms emi energy may enter wherever there is an impedance mismatch or discontinuity in a system. in general this occurs at the interface where cables carrying sensitive analog signals are connected to pc boards, and through power supply leads. improperly connected cables or poor supply filtering schemes are often perfect conduits for interference. conducted noise may also be encountered when two or more currents share a common path (impedance). this common path is often a high impedance "ground" connection. if two circuits share this path, noise currents from one will produce noise voltages in the other. steps may be taken to identify potential sources of this interference (see references 1 and 2, plus section 2 of this chapter). figure 9.122 shows some of the general ways noise can enter a circuit from external sources. (cid:139) impedance mismatches and discontinuities (cid:139) common-mode impedance mismatches → differential signals (cid:139) capacitively coupled (electric field interference) (cid:122) dv/dt → mutual capacitance → noise current (example: 1v/ns produces 1ma/pf) (cid:139) inductively coupled (magnetic field) (cid:122) di/dt → mutual inductance → noise voltage (example: 1ma/ns produces 1mv/nh) figure 9.122: how emi finds paths into equipment there is a capacitance between any two conductors separated by a dielectric (air and vacuum are dielectrics, as well as all solid or liquid insulators). if there is a change of voltage on one conductor there will be change of charge on the other, and a displacement current will flow in the dielectric. where either the capacitance or the dv/dt is high, noise is easily coupled. for example, a 1-v/ns rate-of-change gives rise to displacement currents of 1 ma/pf. if changing magnetic flux from current flowing in one circuit couples into another circuit, it will induce an emf in the second circuit. such mutual inductance can be a troublesome source of noise coupling from circuits with high values of di/dt. as an example, a mutual inductance of 1 nh and a changing current of 1 a/ns will induce an emf of 1 v. reducing common-impedance noise steps to be taken to eliminate or reduce noise due to the conduction path sharing of impedances, or common-impedance noise are outlined in figure 9.123. 9.143

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analog-digital conversion (cid:139) common-impedance noise (cid:122) decouple op amp power leads at lf and hf (cid:122) reduce common-impedance (cid:122) eliminate shared paths (cid:139) techniques (cid:122) low impedance electrolytic (lf) and local low inductance (hf) bypasses (cid:122) use ground and power planes (cid:122) optimize system design figure 9.123: some solutions to common-impedance noise these methods should be applied in conjunction with all of the related techniques discussed earlier within section 2 of this chapter. power supply rails feeding several circuits are good common-impedance examples. real world power sources may exhibit low output impedance, or may they not—especially over frequency. furthermore, pcb traces used to distribute power are both inductive and resistive, and may also form a ground loop. the use of power and ground planes also reduces the power distribution impedance. these dedicated conductor layers in a pcb are continuous (ideally, that is) and as such, offer the lowest practical resistance and inductance. in some applications where low-level signals encounter high levels of common- impedance noise it will not be possible to prevent interference and the system architecture may need to be changed. possible changes include: 1. transmitting signals in differential form 2. amplifying signals to higher levels for improved s/n 3. converting signals into currents for transmission 4. converting signals directly into digital form noise induced by near-field interference crosstalk is the second most common form of interference. in the vicinity of the noise source, i.e., near-field, interference is not transmitted as an electromagnetic wave, and the term crosstalk may apply to either inductively or capacitively coupled signals. reducing capacitance-coupled noise capacitively-coupled noise may be reduced by reducing the coupling capacity (by increasing conductor separation), but is most easily cured by shielding. a conductive and grounded shield (known as a faraday shield) between the signal source and the affected node will eliminate this noise, by routing the displacement current directly to ground. with the use of such shields, it is important to note that it is always essential that a faraday shield be grounded. a floating or open-circuit shield almost invariably increases 9.144

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hardware design techniques 9.6 emi/rfi considerations capacitively-coupled noise. for a brief review of this shielding, consult section 2 of this chapter again, and see references 2 and 3 at the end of this section. methods to eliminate capacitance-coupled interference are summarized in figure 9.124. (cid:139) reduce level of high dv/dt noise sources (cid:139) use proper grounding schemes for cable shields (cid:139) reduce stray capacitance (cid:122) equalize input lead lengths (cid:122) keep traces short (cid:122) use signal-ground signal-routing schemes (cid:139) use grounded conductive faraday shields to protect against electric fields figure 9.124: methods to reduce capacitance-coupled noise reducing magnetically-coupled noise methods to eliminate interference caused by magnetic fields are summarized in figure 9.125. (cid:139) careful routing of wiring (cid:139) use conductive screens for hf magnetic shields (cid:139) use high permeability shields for lf magnetic fields (mu-metal) (cid:139) reduce loop area of receiver (cid:122) twisted pair wiring (cid:122) physical wire placement (cid:122) orientation of circuit to interference (cid:139) reduce noise sources (cid:122) twisted pair wiring (cid:122) driven shields figure 9.125: methods to reduce magnetically-coupled noise to illustrate the effect of magnetically-coupled noise, consider a circuit with a closed- loop area of a cm2 operating in a magnetic field with an rms flux density value of b gauss. the noise voltage vn induced in this circuit can be expressed by the following equation: vn = 2 π f b a cosθ × 10–8 v eq. 9.12 in this equation, f represents the frequency of the magnetic field, and θ represents the angle of the magnetic field b to the circuit with loop area a. magnetic field coupling can be reduced by reducing the circuit loop area, the magnetic field intensity, or the angle of 9.145

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analog-digital conversion incidence. reducing circuit loop area requires arranging the circuit conductors closer together. twisting the conductors together reduces the loop net area. this has the effect of canceling magnetic field pickup, because the sum of positive and negative incremental loop areas is ideally equal to zero. reducing the magnetic field directly may be difficult. however, since magnetic field intensity is inversely proportional to the cube of the distance from the source, physically moving the affected circuit away from the magnetic field has a very great effect in reducing the induced noise voltage. finally, if the circuit is placed perpendicular to the magnetic field, pickup is minimized. if the circuit's conductors are in parallel to the magnetic field the induced noise is maximized because the angle of incidence is zero. there are also techniques that can be used to reduce the amount of magnetic-field interference, at its source. in the previous paragraph, the conductors of the receiver circuit were twisted together, to cancel the induced magnetic field along the wires. the same principle can be used on the source wiring. if the source of the magnetic field is large currents flowing through nearby conductors, these wires can be twisted together to reduce the net magnetic field. shields and cans are not nearly as effective against magnetic fields as against electric fields, but can be useful on occasion. at low frequencies magnetic shields using high- permeability material such as mu-metal can provide modest attenuation of magnetic fields. at high frequencies simple conductive shields are quite effective provided that the thickness of the shield is greater than the skin depth of the conductor used (at the frequency involved). note—copper skin depth is 6.6/√f cm, with f in hz. passive components: your arsenal against emi passive components, such as resistors, capacitors, and inductors, are powerful tools for reducing externally induced interference when used properly. simple rc networks make efficient and inexpensive one-pole, low-pass filters. incoming noise is converted to heat and dissipated in the resistor. but note that a fixed resistor does produce thermal noise of its own. also, when used in the input circuit of an op amp or in- amp, such resistor(s) can generate input-bias-current induced offset voltage. while matching the two resistors will minimize the dc offset, the noise will remain. figure 9.126 summarizes some popular low-pass filters for minimizing emi. in applications where signal and return conductors aren't well-coupled magnetically, a common-mode (cm) choke can be used to increase their mutual inductance. note that these comments apply mostly to in-amps, which naturally receive a balanced input signal (whereas op amps are inherently unbalanced inputs—unless one constructs an in-amp with them). a cm choke can be simply constructed by winding several turns of the differential signal conductors together through a high-permeability (> 2000) ferrite bead. the magnetic properties of the ferrite allow differential-mode currents to pass unimpeded while suppressing cm currents. 9.146

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lp filter type advantage rc section simple inexpensive hardware design techniques 9.6 emi/rfi considerations disadvantage resistor thermal noise ib x r drop → offset single-pole cutoff lc section (bifilar) very low noise at lf medium complexity very low ir drop nonlinear core effects possible inexpensive two-pole cutoff π section (c-l-c) very low noise at lf most complex very low ir drop nonlinear core effects possible pre-packaged filters multiple-pole cutoff expensive figure 9.126: using passive components within filters to combat emi capacitors can also be used before and after the choke, to provide additional cm and differential-mode filtering, respectively. such a cm choke is cheap and produces very low thermal noise and bias current-induced offsets, due to the wire's low dc resistance. however, there is a field around the core. a metallic shield surrounding the core may be necessary to prevent coupling with other circuits. also, note that high-current levels should be avoided in the core as they may saturate the ferrite. the third method for passive filtering takes the form of packaged π-networks (c-l-c). these packaged filters are completely self-contained and include feedthrough capacitors at the input and the output as well as a shield to prevent the inductor's magnetic field from radiating noise. these more expensive networks offer high levels of attenuation and wide operating frequency ranges, but the filters must be selected so that for the operating current levels involved the ferrite doesn’t saturate. reducing system susceptibility to emi the general examples discussed above and the techniques illustrated earlier in this section outline the procedures that can be used to reduce or eliminate emi/rfi. considered on a system basis, a summary of possible measures is given in figure 9.127. other examples of filtering techniques useful against emi are illustrated later in this section, under "reducing rfi rectification within op amp and in-amp circuits". the section immediately below further details shielding principles. 9.147

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analog-digital conversion (cid:139) always assume that interference exists! (cid:139) use conducting enclosures against electric and hf magnetic fields (cid:139) use mu-metal enclosures against lf magnetic fields (cid:139) implement cable shields effectively (cid:139) use feedthrough capacitors and packaged pi filters figure 9.127: reducing system emi/rfi susceptibility a review of shielding concepts the concepts of shielding effectiveness presented next are background material. interested readers should consult references 4-9 cited at the end of the section for more detailed information. applying the concepts of shielding effectively requires an understanding of the source of the interference, the environment surrounding the source, and the distance between the source and point of observation (the receiver). if the circuit is operating close to the source (in the near, or induction-field), then the field characteristics are determined by the source. if the circuit is remotely located (in the far, or radiation-field), then the field characteristics are determined by the transmission medium. a circuit operates in a near-field if its distance from the source of the interference is less than the wavelength (λ) of the interference divided by 2π, or λ/2π. if the distance between the circuit and the source of the interference is larger than this quantity, then the circuit operates in the far field. for instance, the interference caused by a 1-ns pulse edge has an upper bandwidth of approximately 350 mhz. the wavelength of a 350-mhz signal is approximately 32 inches (the speed of light is approximately 12"/ns). dividing the wavelength by 2π yields a distance of approximately 5 inches, the boundary between near- and far-field. if a circuit is within 5 inches of a 350-mhz interference source, then the circuit operates in the near-field of the interference. if the distance is greater than 5 inches, the circuit operates in the far-field of the interference. regardless of the type of interference, there is a characteristic impedance associated with it. the characteristic, or wave impedance of a field is determined by the ratio of its electric (or e-) field to its magnetic (or h-) field. in the far field, the ratio of the electric field to the magnetic field is the characteristic (wave impedance) of free space, given by zo = 377 ω. in the near field, the wave-impedance is determined by the nature of the interference and its distance from the source. if the interference source is high-current and low-voltage (for example, a loop antenna or a power-line transformer), the field is predominately magnetic and exhibits a wave impedance which is less than 377 ω. if the source is low-current and high-voltage (for example, a rod antenna or a high-speed digital switching circuit), then the field is predominately electric and exhibits a wave impedance which is greater than 377 ω. 9.148

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hardware design techniques 9.6 emi/rfi considerations conductive enclosures can be used to shield sensitive circuits from the effects of these external fields. these materials present an impedance mismatch to the incident interference, because the impedance of the shield is lower than the wave impedance of the incident field. the effectiveness of the conductive shield depends on two things: first is the loss due to the reflection of the incident wave off the shielding material. second is the loss due to the absorption of the transmitted wave within the shielding material. the amount of reflection loss depends upon the type of interference and its wave impedance. the amount of absorption loss, however, is independent of the type of interference. it is the same for near- and far-field radiation, as well as for electric or magnetic fields. reflection loss at the interface between two media depends on the difference in the characteristic impedances of the two media. for electric fields, reflection loss depends on the frequency of the interference and the shielding material. this loss can be expressed in db, and is given by: ( ) re db = 322 + 10log10     r σ r f 3 r2 µ     eq. 9.13 where σr = relative conductivity of the shielding material, in siemens per meter; µr = relative permeability of the shielding material, in henries per meter; f = frequency of the interference, and r = distance from source of the interference, in meters for magnetic fields, the loss depends also on the shielding material and the frequency of the interference. reflection loss for magnetic fields is given by: r m db = 14.6 + 10log10 ( ) σ r f r2 µ r         eq. 9.14 and, for plane waves ( r > λ/2π), the reflection loss is given by: r pw db = 168 + 10log10 ( )    σ r µ r f    eq. 9.15 absorption is the second loss mechanism in shielding materials. wave attenuation due to absorption is given by: )db(a = t34.3 rµσ f r eq. 9.16 where t = thickness of the shield material, in inches. this expression is valid for plane waves, electric and magnetic fields. since the intensity of a transmitted field decreases exponentially relative to the thickness of the shielding material, the absorption loss in a shield one skin-depth (δ) thick is 9 db. since absorption loss is proportional to thickness and inversely proportional to skin depth, increasing the thickness of the shielding material improves shielding effectiveness at high frequencies. 9.149

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analog-digital conversion reflection loss for plane waves in the far field decreases with increasing frequency because the shield impedance, zs, increases with frequency. absorption loss, on the other hand, increases with frequency because skin depth decreases. for electric fields and plane waves, the primary shielding mechanism is reflection loss, and at high frequencies, the mechanism is absorption loss. thus for high-frequency interference signals, lightweight, easily worked high conductivity materials such as copper or aluminum can provide adequate shielding. at low frequencies however, both reflection and absorption loss to magnetic fields is low. it is thus very difficult to shield circuits from low-frequency magnetic fields. in these applications, high-permeability materials that exhibit low-reluctance provide the best protection. these low-reluctance materials provide a magnetic shunt path that diverts the magnetic field away from the protected circuit. to summarize the characteristics of metallic materials commonly used for shielded purposes: use high conductivity metals for hf interference, and high permeability metals for lf interference. a properly shielded enclosure is very effective at preventing external interference from disrupting its contents as well as confining any internally-generated interference. however, in the real world, openings in the shield are often required to accommodate adjustment knobs, switches, connectors, or to provide ventilation. unfortunately, these openings may compromise shielding effectiveness by providing paths for high-frequency interference to enter the instrument. the longest dimension (not the total area) of an opening is used to evaluate the ability of external fields to enter the enclosure, because the openings behave as slot antennas. equation eq. 9.17 can be used to calculate the shielding effectiveness, or the susceptibility to emi leakage or penetration, of an opening in an enclosure: shielding effectiven ess )db( = 20 log 10    λ ⋅ l2    eq. 9.17 where λ = wavelength of the interference and l = maximum dimension of the opening maximum radiation of emi through an opening occurs when the longest dimension of the opening is equal to one half-wavelength of the interference frequency (0-db shielding effectiveness). a rule-of-thumb is to keep the longest dimension less than 1/20 wavelength of the interference signal, as this provides 20-db shielding effectiveness. furthermore, a few small openings on each side of an enclosure is preferred over many openings on one side. this is because the openings on different sides radiate energy in different directions, and as a result, shielding effectiveness is not compromised. if openings and seams cannot be avoided, then conductive gaskets, screens, and paints alone or in combination should be used judiciously to limit the longest dimension of any opening to less than 1/20 wavelength. any cables, wires, connectors, indicators, or control shafts penetrating the enclosure should have circumferential metallic shields 9.150

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hardware design techniques 9.6 emi/rfi considerations physically bonded to the enclosure at the point of entry. in those applications where unshielded cables/wires are used, then filters are recommended at the shield entry point. general points on cables and shields although covered in detail elsewhere, it is worth noting that the improper use of cables and their shields can be a significant contributor to both radiated and conducted interference. rather than developing an entire treatise on these issues, the interested reader should consult references 2, 3, 5, and 6 for background. as shown in figure 9.128, proper cable/enclosure shielding confines sensitive circuitry and signals entirely within the shield, with no compromise to shielding effectiveness. shielded shielded shielded shielded shielded shielded enclosure a enclosure a interconnect interconnect enclosure b enclosure b cable cable length = l length = l fully shielded enclosures connected by fully fully shielded enclosures connected by fully shielded cable keep all internal circuits and shielded cable keep all internal circuits and signal lines inside the shield. signal lines inside the shield. transition region: 1/20 wavelength transition region: 1/20 wavelength figure 9.128: shielded interconnect cables are either electrically long or short, depending upon the operating frequency as can be noted by this diagram, the enclosures and the shield must be grounded properly, otherwise they can act as an antenna, thereby making the radiated and conducted interference problem worse (rather than better). depending on the type of interference (pickup/radiated, low/high frequency), proper cable shielding is implemented differently and is very dependent on the length of the cable. the first step is to determine whether the length of the cable is electrically short or electrically long at the frequency of concern. a cable is considered electrically short if the length of the cable is less than 1/20 wavelength of the highest frequency of the interference. otherwise it is considered to be electrically long. for example, at 50/60 hz, an electrically short cable is any cable length less than 150 miles, where the primary coupling mechanism for these low frequency electric fields is capacitive. as such, for any cable length less than 150 miles, the amplitude of the interference will be the same over the entire length of the cable. 9.151

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analog-digital conversion in applications where the length of the cable is electrically long, or protection against high-frequency interference is required, then the preferred method is to connect the cable shield to low-impedance points, at both ends. as will be seen shortly, this can be a direct connection at the driving end, and a capacitive connection at the receiver. if left ungrounded, unterminated transmission lines effects can cause reflections and standing waves along the cable. at frequencies of 10 mhz and above, circumferential (360°) shield bonds and metal connectors are required to main low-impedance connections to ground. in summary, for protection against low-frequency (<1 mhz), electric-field interference, grounding the shield at one end is acceptable. for high-frequency interference (>1 mhz), the preferred method is grounding the shield at both ends, using 360° circumferential bonds between the shield and the connector, and maintaining metal-to-metal continuity between the connectors and the enclosure. however in practice, there is a caveat involved with directly grounding the shield at both ends. when this is done, it creates a low frequency ground loop, shown in figure 9.129. a1 a1 in in a2 a2 gnd 1 gnd 1 vn vn gnd 2 gnd 2 (cid:139) vn causes current in shield (usually 50/60hz) (cid:139) vn causes current in shield (usually 50/60hz) (cid:139) differential error voltage is produced at input of a2 unless: (cid:139) differential error voltage is produced at input of a2 unless: (cid:122) a1 output is perfectly balanced and (cid:122) a1 output is perfectly balanced and (cid:122) a2 input is perfectly balanced and (cid:122) a2 input is perfectly balanced and (cid:122) cable is perfectly balanced (cid:122) cable is perfectly balanced figure 9.129: ground loops in shielded twisted pair cable can cause errors whenever two systems a1 and a2 are remote from each other, there is usually a difference in the ground potentials at each system, i.e., vn. the frequency of this potential difference is generally the line frequency (50 or 60 hz) and multiples thereof. but, if the shield is directly grounded at both ends as shown, noise current in flows in the shield. in a perfectly balanced system, the common-mode rejection of the system is infinite, and this current flow produces no differential error at the receiver a2. however, perfect balance is never achieved in the driver, its impedance, the cable, or the receiver, so a certain portion of the shield current will appear as a differential noise signal, at the input of a2. the following illustrate correct shield grounding for various examples. 9.152

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hardware design techniques 9.6 emi/rfi considerations as noted above, cable shields are subject to both low and high frequency interference. good design practice requires that the shield be grounded at both ends if the cable is electrically long to the interference frequency, as is usually the case with rf interference. figure 9.130 shows a remote passive rtd sensor connected to a bridge and conditioning circuit by a shielded cable. the proper grounding method is shown in the upper part of the figure, where the shield is grounded at the receiving end. rtd rtd nc nc rtd rtd bridge bridge and and conditioning conditioning circuits circuits bridge bridge and and conditioning conditioning circuits circuits “hybrid” “hybrid” ground ground c c figure 9.130: hybrid grounding of shielded cable with passive sensor however, safety considerations may require that the remote end of the shield also be grounded. if this is the case, the receiving end can be grounded with a low inductance ceramic capacitor (0.01 µf to 0.1 µf), still providing high frequency grounding. the capacitor acts as a ground to rf signals on the shield but blocks low frequency line current to flow in the shield. this technique is often referred to as a hybrid ground. a case of an active remote sensor and/or other electronics is shown figure 9.131. in both of the two situations, a hybrid ground is also appropriate, either for the balanced (upper) or the single-ended (lower) driver case. in both instances the capacitor "c" breaks the low frequency ground loop, providing effective rf grounding of the shielded cable at the a2 receiving end at the right side of the diagram. there are also some more subtle points that should be made with regard to the source termination resistances used, rs. in both the balanced as well as the single-ended drive cases, the driving signal seen on the balanced line originates from a net impedance of rs, which is split between the two twisted pair legs as twice rs/2. in the upper case of a fully differential drive, this is straightforward, with an rs/2 valued resistor connected in series with the complementary outputs from a1. 9.153

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hardware design techniques 9.6 emi/rfi considerations coax cable coax cable a1 a1 a1 a1 shield carries signal return current shield carries signal return current a2 a2 a2 a2 diff diff amp amp single- single- ended ended amp amp figure 9.132: coaxial cables can use either balanced or single-ended receivers input-stage rfi rectification sensitivity a well-known but poorly understood phenomenon in analog integrated circuits is rfi rectification, specifically as it occurs in op amps and in-amps. while amplifying very small signals these devices can rectify large-amplitude, out-of-band hf signals, i.e., rfi. as a result, dc errors appear at the output in addition to the desired signal. the undesired hf signals can enter sensitive analog circuits by various means. conductors leading into and out of the circuit provide a path for interference coupling into a circuit. these conductors pick up noise through capacitive, inductive, or radiation coupling, as discussed earlier. the spurious signals appear at the amplifier inputs, along with the desired signal. the spurious signals can be several tens of mv in amplitude however, which causes problems. simply stated, it cannot be assumed that a sensitive, low- bandwidth dc amplifier will always reject out-of-band spurious signals. while this would be the case for a simple linear low pass filter, op amp and in-amp devices actually rectify high-level hf signals, leading to non-linearities and anomalous offsets. methods of analysis for as well as the prevention of rfi rectification are discussed in this section. background: op amp and in-amp rfi rectification sensitivity tests just about all in-amp and op amp input stages use emitter-coupled bjt or source-coupled fet differential pairs of some type. depending on the device operating current, the interfering frequency and its relative amplitude, these differential pairs can behave as high-frequency detectors. as will be shown, the detection process produces spectral components at the harmonics of the interference, as well at dc! it is the detected dc component of the interference that shifts amplifier bias levels, leading to inaccuracies. 9.155

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analog-digital conversion the effect of rfi rectification within op amps and in-amps can be evaluated with relatively simple test circuits, as described for the rfi rectification test configuration (see page 1-38 of reference 10). in these tests, an op amp or in-amp is configured for a gain of –100 (op amp), or 100 (in-amp), with dc output measured after a 100-hz low-pass filter, preventing interference from other signals. a 100-mhz, 20-mvp-p signal is the test stimulus, chosen to be well above test device frequency limits. in operation, the test evaluates dc output shift observed under stimulus presence. while an ideal dc shift for this measurement would be zero, the actual dc shift of a given part indicates the relative rfi rectification sensitivity. devices using both bjt and fet technologies can be tested by this method, as can devices operating at either low or high supply current levels. in the original op amp test device set of reference 10, some fet-input devices (op80, op42, op249 and ad845) exhibited no observable shift in their output voltages, while several others showed shifts of less than 10 µv referred to the input. of the bjt-input op amps, the amount of shift decreased with increasing device supply current. only two devices showed no observable output voltage shift (ad797 and ad827), while others showed shifts of less than 10 µv referred to the input (op200 and op297). for other op amps, it is to be expected that similar patterns would be shown under such testing. from these tests, some generalizations on rfi rectification can be made. first, device susceptibility appears to be inversely proportional to supply current; that is, devices biased at low quiescent supply currents exhibit greatest output voltage shift. second, ics with fet-input stages appeared to be less susceptible to rectification than those with bjts. note that these points are independent of whether the device is an op amp or an in- amp. in practice this means that the lower power op amps or in-amps will tend to be more susceptible to rfi rectification effects. and, fet-input op amps (or in-amps) will tend to be less susceptible to rfi, especially those operating at higher currents. based on these data and from the fundamental differences between bjts and fets, we can summarize what we know. bipolar transistor action is controlled by a forward-biased p-n junction (the base-emitter junction) whose i-v characteristic is exponential and quite nonlinear. fet behavior, on the other hand, is controlled by voltages applied to a reverse- biased p-n junction diode (the gate-source junction). the i-v characteristic of fets is a square-law, and thus it is inherently more linear than that of bjts. for the case of the lower supply current devices, transistors in the circuit are biased well below their peak ft collector currents. although the ics may be constructed on processes whose device fts can reach hundreds of mhz, charge transit times increase, when transistors are operated at low current levels. the impedance levels used also make rfi rectification in these devices worse. in low-power op amps, impedances are on the order of hundreds to thousands of kωs, whereas in moderate supply-current designs impedances might be no more than just a few kω. combined, these factors tend to degrade a low-power device's rfi rectification sensitivity. figure 9.133 summarizes these general observations on rfi rectification sensitivity, and is applicable to both op amps and in-amps. 9.156

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hardware design techniques 9.6 emi/rfi considerations (cid:139)bjt input devices rectify readily (cid:122) forward-biased b-e junction (cid:122) exponential i-v transfer characteristic (cid:139)fet input devices less sensitive to rectifying (cid:122) reversed-biased p-n junction (cid:122) square-law i-v transfer characteristic (cid:139)low isupply devices versus high isupply devices (cid:122) low isupply ⇒ higher rectification sensitivity (cid:122) high isupply ⇒ lower rectification sensitivity figure 9.133: some general observations on op amp and in-amp input stage rfi rectification sensitivity an analytical approach: bjt rfi rectification while lab experiments can demonstrate that bjt-input devices exhibit greater rfi rectification sensitivity than comparable devices with fet inputs, a more analytical approach can also be taken to explain this phenomenon. rf circuit designers have long known that p-n junction diodes are efficient rectifiers because of their nonlinear i-v characteristics. a spectral analysis of a bjt transistor current output for a hf sinewave input reveals that, as the device is biased closer to its "knee," nonlinearity increases. this, in turn, makes its use as a detector more efficient. this is especially true in low-power op amps, where input transistors are biased at very low collector currents. a rectification analysis for the collector current of a bjt has been presented in reference 10, and will not be repeated here except for the important conclusions. these results reveal that the original quadratic second-order term can be simplified into a frequency- dependent term, ∆ic(ac), at twice the input frequency and a dc term, ∆ic(dc). the latter component can be expressed as noted in eq. 9.18, the final form for the rectified dc term: ) ∆ =dcci (    xv tv 2  •  ci 4 eq. 9.18 this expression shows that the dc component of the second-order term is directly proportional to the square of the hf noise amplitude vx, and, also, to ic, the quiescent collector current of the transistor. to illustrate this point on rectification, note that the change in dc collector current of a bipolar transistor operating at an ic of 1 ma with a spurious 10-mvpeak high-frequency signal impinging upon it will be about 38 µa. reducing the amount of rectified collector current is a matter of reducing the quiescent current, or the magnitude of the interference. since the op amp and in-amp input stages seldom provide adjustable quiescent collector currents, reducing the level of interfering noise vx is by far the best (and almost always the only) solution. for example, reducing the amplitude of the interference by a factor of 2, down to 5 mvpeak produces a net 4 to 1 9.157

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analog-digital conversion reduction in the rectified collector current. obviously, this illustrates the importance of keeping spurious hf signals away from rfi sensitive amplifier inputs. an analytical approach: fet rfi rectification a rectification analysis for the drain current of a jfet has also been presented in reference 10, and isn’t repeated here. a similar approach was used for the rectification analysis of a fet's drain current as a function of a small voltage vx, applied to its gate. the results of evaluating the second-order rectified term for the fet's drain current are summarized in eq. 9.19. like the bjt, an fet's second-order term has an ac and a dc component. the simplified expression for the dc term of the rectified drain current is given here, where the rectified dc drain current is directly proportional to the square of the amplitude of vx, the spurious signal. however, eq. 9.19 also reveals a very important difference between the degree of the rectification produced by fets relative to bjts. ) ∆ =dcdi (    xv pv 2  •  i dss 2 eq. 9.19 whereas in a bjt the change in collector current has a direct relationship to its quiescent collector current level, the change in a jfet's drain current is proportional to its drain current at zero gate-source voltage, idss, and inversely proportional to the square of its channel pinch-off voltage, vp—parameters that are geometry and process dependent. typically, jfets used in the input stages of in-amps and op amps are biased with their quiescent current of ~0.5 · idss. therefore, the change in a jfet's drain current is independent of its quiescent drain current; hence, independent of the operating point. a quantitative comparison of second-order rectified dc terms between bjts and fets is illustrated in figure 9.134. in this example, a bipolar transistor with a unit emitter area of 576 µm2 is compared to a unit-area jfet designed for an idss of 20 µa and a pinch-off voltage of 2 v. each device is biased at 10 µa and operated at ta = 25°c. the important result is that, under identical quiescent current levels, the change in collector current in bipolar transistors is about 1500 times greater than the change in a jfet's drain current. this explains why fet-input amplifiers behave with less sensitivity to large amplitude hf stimulus. as a result, they offer more rfi rectification immunity. what all this boils down to is this: since a user has virtually no access to the amplifier’s internal circuitry, the prevention of ic circuit performance degradation due to rfi is left essentially to those means which are external to the ics. as the analysis above shows, regardless of the amplifier type, rfi rectification is directly proportional to the square of the interfering signal’s amplitude. therefore, to minimize rfi rectification in precision amplifiers, the level of interference must be reduced or eliminated, prior to the stage. the most direct way to reduce or eliminate the unwanted noise is by proper filtering. this topic is covered in the section immediately following. 9.158

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hardware design techniques 9.6 emi/rfi considerations (cid:139) bjt: (cid:139) bjt: (cid:139) jfet: (cid:139) jfet: emitter area = 576µm2 emitter area = 576µm2 ic = 10µa ic = 10µa vt = 25.68mv @ 25°c vt = 25.68mv @ 25°c     =∆ =∆   i i c c v v x x v v t t 2 2   • •   i i c c 4 4 2 2 v v x= x= 264 264 idss = 20µa (z/l=1) idss = 20µa (z/l=1) vp = 2v vp = 2v id id = 10µa = 10µa     =∆ =∆   i i d d v v x x v v p p 2 2   • •   i i dss dss 2 2 2 2 v v x x = = 3 3 400x10 400x10 (cid:139) conclusion: bjts ~1500 more sensitive than jfets! (cid:139) conclusion: bjts ~1500 more sensitive than jfets! figure 9.134: relative sensitivity comparison - bjt versus jfet reducing rfi rectification within op amp and in-amp circuits emi and rfi can seriously affect the dc performance of high accuracy analog circuits. because of their relatively low bandwidth, precision op amps and in-amps simply won’t accurately amplify rf signals in the mhz range. however, if these out-of-band signals are allowed to couple into a precision amplifier through either its input, output, or power supply pins, they can be internally rectified by various amplifier junctions, ultimately causing an undesirable dc offset at the output. the previous theoretical discussion of this phenomenon has shown its basic mechanisms. the logical next step is to show how proper filtering can minimize or eliminate these errors. elsewhere in this chapter we have discussed how proper supply decoupling minimizes rfi on ic power pins. further discussion is required with respect to the amplifier inputs and outputs, at the device level. it is assumed at this point that system level emi/rfi approaches have already been implemented, such as an rfi-tight enclosure, properly grounded shields, power rail filtering, etc. the steps following can be considered as circuit-level emi/rfi prevention. op amp inputs the best way to prevent input stage rectification is to use a low-pass filter located close to the op amp input as shown in figure 9.135. in the case of the inverting op amp at the left, filter capacitor c is placed between equal-value resistors r1-r2. this results in a simple corner frequency expression, as shown in the figure. at very low frequencies or dc, the closed loop gain of the circuit is –r3/(r1+r2). note that c cannot be connected directly to the inverting input of the op amp, since that would cause instability. the filter bandwidth can be chosen at least 100 times the signal bandwidth to minimize signal loss. 9.159

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analog-digital conversion r1 = 2r r2 = 2r r1 = 2r r2 = 2r r3 r3 r1 = r r1 = r r1 = r c cc _ _ + + c c c + + + _ _ _ r3 r3 r3 r2 r2 r2 emi filter bandwidth = emi filter bandwidth = emi filter bandwidth = > 100× signal bandwidth > 100× signal bandwidth > 100× signal bandwidth 1 1 1 2π r c 2π r c 2π r c figure 9.135: simple emi/rfi noise filters for op amp circuits for the non-inverting case on the right, capacitor c can be connected directly to the op amp input as shown, and an input resistor with a value "r" yields the same corner frequency as the inverting case. in both cases low inductance chip-style capacitors should be used, such as np0 ceramics. the capacitor should in any case be free of losses or voltage coefficient problems, which limits it to either the np0 mentioned, or a film type. it should be noted that a ferrite bead can be used instead of r1, however ferrite bead impedance is not well controlled and is generally no greater than 100 ω at 10 mhz to 100 mhz. this requires a large value capacitor to attenuate lower frequencies. in-amp inputs precision in-amps are particularly sensitive to dc offset errors due to the presence of cm emi/rfi. this is very much like the problem in op amps. and, as is true with op amps, the sensitivity to emi/rfi is more acute with the lower power in-amp devices. a general-purpose approach to proper filtering for device level application of in-amps is shown in figure 9.136. in this circuit the in-amp could in practice be any one of a number of devices. the relatively complex balanced rc filter preceding the in-amp performs all of the high frequency filtering. the in-amp would be programmed for the gain required in the application, via its gain-set resistance (not shown). within the filter, note that fully balanced filtering is provided for both cm (r1-c1 and r2-c2) as well as differential mode (dm) signals (r1+r2, and c3 || the series connection of c1-c2). if r1-r2 and c1-c2 aren't well matched, some of the input common-mode signal at vin will be converted to a differential mode signal at the in-amp inputs. for this reason, c1 and c2 should be matched to within at least 5% of each other. also, r1 and r2 should be 1% metal film resistors, so as to aid this matching. it is assumed that the source resistances seen at the vin terminals are low with respect to r1-r2, and matched. in this type of filter, c3 should be chosen much larger than c1 or c2 (c3 ≥ c1, c2), in order to suppress spurious differential signals due to cm⇒dm conversion resulting from mismatch of the r1-c1 and r2-c2 time constants. 9.160

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hardware design techniques 9.6 emi/rfi considerations r1 r1 r2 r2 c1 c1 c2 c2 vin vin + + c3 c3 in-amp in-amp vout vout _ _ τdiff = (r1 + r2) τdiff = (r1 + r2) τcm = r1 c1 = r2 c2 τcm = r1 c1 = r2 c2 τdiff >> τcm τdiff >> τcm c1·c2 c1·c2 c1 + c2 + c3 c1 + c2 + c3 r1 c1 = r2 c2 r1 c1 = r2 c2 r1 = r2 should be 1% resistors r1 = r2 should be 1% resistors c1 = c2 should be ≤ 5% capacitors c1 = c2 should be ≤ 5% capacitors 1 1 differential differential filter bandwidth filter bandwidth = = 2π (r1 + r2) 2π (r1 + r2) c1·c2 c1·c2 c1 + c2 + c3 c1 + c2 + c3 figure 9.136: a general-purpose common-mode/differential-mode rc emi/rfi filter for in-amps the overall filter bandwidth should be at least 100 times the input signal bandwidth. physically, the filter components should be symmetrically mounted on a pc board with a large area ground plane and placed close to the in-amp inputs for optimum performance. figure 9.137 shows a family of these filters, as suited to a range of different in-amps. the rc components should be tailored to the different in-amp devices, as per the table. these filter components are selected for a reasonable balance of low emi/rfi sensitivity and a low increase in noise (vis-à-vis that of the related in-amp, without the filter). 50ω 50ω sinewave sinewave source source vin vin rf cm test rf cm test dc - 20mhz dc - 20mhz 1v p-p 1v p-p r1 r1 r2 r2 c1 c1 c2 c2 c3 c3 rg rg + + _ _ u1 u1 vout vout u1 u1 r1/r2 r1/r2 1% 1% c1/c2 c3 c1/c2 c3 ≤ 5% 10% ≤ 5% 10% ad620/621/622 4.02k 1nf 47nf ad620/621/622 4.02k 1nf 47nf ad623 10k 1nf 22nf ad623 10k 1nf 22nf ad627 20k 1nf 22nf ad627 20k 1nf 22nf figure 9.137: flexible common-mode and differential-mode rc emi/rfi filters are useful with the ad620 series, the ad623, ad627, and other in-amps 9.161

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analog-digital conversion to test the emi/rfi sensitivity of the configuration, a 1-vp-p cm signal can be applied to the input resistors, as noted. with a typically used in-amp such as the ad620 working at a gain of 1000, the maximum rti input offset voltage shift observed was 1.5 µv over the 20-mhz range. in the ad620 filter example, the differential bandwidth is about 400 hz. common-mode chokes offer a simple, one-component emi/rfi protection alternative to the passive rc filters, as shown in figure 9.138. 50ω 50ω sinewave sinewave source source rf cm test rf cm test dc - 20mhz dc - 20mhz 1v p-p 1v p-p vin vin rg rg + + ad620 ad620 ad621 ad621 ad622 ad622 _ _ vout vout (cid:139) common mode choke: (cid:139) common mode choke: pulse engineering b4001 pulse engineering b4001 http://www.pulseeng.com http://www.pulseeng.com figure 9.138: for simplicity as well as lowest noise emi/rfi filter operation, a common-mode choke is useful with the ad620 series in-amp devices in addition to being a low component count approach, choke-based filters offer low noise, by dispensing with the resistances. selecting the proper common-mode choke is critical, however. the choke used in the circuit of figure 9.138 is a pulse engineering b4001. the maximum rti offset shift measured from dc to 20 mhz at g = 1000 was 4.5 µv. either an off-the-shelf choke such as the b4001 can be used for this filter, or, alternately one can be constructed. since balance of the windings is important, bifilar wire is suggested. the core material must of course operate over the expected frequency band. note that, unlike the figure 9.137 family of rc filters, a choke-only filter offers no differential filtration. differential mode filtering can be optionally added, with a second stage following the choke, by adding the r1-c3-r2 connections of figure 9.137. for further information on in-amp emi/rfi filtering, see references 10, and 12 - 15. amplifier outputs and emi/rfi in addition to filtering the input and power pins, amplifier outputs also need to be protected from emi/rfi, especially if they must drive long lengths of cable, which act as antennas. rf signals received on an output line can couple back into the amplifier input where it is rectified, and appears again on the output as an offset shift. 9.162

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a resistor and/or ferrite bead, or both, in series with the output is the simplest and least expensive output filter, as shown in figure 9.139 (upper circuit). hardware design techniques 9.6 emi/rfi considerations amp amp amp amp r1 r1 100ω 100ω r1 r1 100ω 100ω r2 r2 100ω 100ω c c 1nf 1nf vout vout resistor or resistor or ferrite bead ferrite bead (or both) (or both) vout vout rc “t” filter rc “t” filter figure 9.139: op amp and in-amp outputs should be protected against emi/rfi, particularly if they drive long cables adding a resistor-capacitor-resistor "t" circuit as shown in figure 9.139 (lower circuit) improves this filter with just slightly more complexity. the output resistor and capacitor divert most of the high frequency energy away from the amplifier, making this configuration useful even with low power active devices. of course, the time constant of the filter parts must be chosen carefully, to minimize any degradation of the desired output signal. in this case the rc components are chosen for an approximate 3-mhz signal bandwidth, suitable for instrumentation or other low bandwidth stages. printed circuit board design for emi/rfi protection this section summarizes general points on emi/rfi with respect to the printed circuit board (pcb) layout. it complements earlier chapter discussions on general pcb design techniques. when a pcb design has not been optimized in terms of emi/rfi, system performance can be compromised. this is true not only for signal-path performance, but also for the system’s susceptibility to emi, plus the degree of emi radiated by the system. failure to implement sound pcb layout techniques will very likely lead to system/instrument emc failures. to summarize earlier points of this section, a real-world pcb layout may allow multiple paths through which high-frequency noise can couple/radiate into and/or out of the circuit. this is especially true for digital circuitry, operating at high edge rates. it is the rapid changes of logic state (1 ⇒ 0 or 0 ⇒ 1), i.e., the edge rate which contains the hf energy which can easily radiate as emi. while similar points are applicable to precision high-speed analog or mixed analog/digital circuits, logic devices are by far the worst potential emi offenders. identifying critical circuits and paths helps in designing the pcb for both low emissions and susceptibility to radiated and conducted external and internal noise sources. 9.163

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analog-digital conversion choose logic devices carefully! logic family speaking, a key point in minimizing system noise problems is to choose devices no faster than actually required by the application. many designers assume that faster is always better—fast logic is better than slow, high bandwidth amplifiers better than low bandwidth ones, and fast dacs and adcs are better, even if the speed isn’t required by the system. unfortunately, faster is not better, and actually may be worse for emi concerns. many fast dacs and adcs have digital inputs and outputs with edge rates in the 1-v/ns region. because of this wide bandwidth, the sampling clock and the digital inputs can respond to any form of high frequency noise, even glitches as narrow as 1 to 3 ns. these high speed data converters and amplifiers are thus easy prey for the high frequency noise of microprocessors, digital signal processors, motors, switching regulators, hand-held radios, electric jackhammers, etc. with some of these high-speed devices, a small amount of input/output filtering may be required to desensitize the circuit from its emi/rfi environment. a ferrite bead just before the local decoupling capacitor is very effective in filtering high frequency noise on supply lines. of course, with circuits requiring bipolar supplies, this technique should be applied to both positive and negative supply lines. to help reduce emissions generated by extremely fast moving digital signals at dac inputs or adc outputs, a small resistor or ferrite bead may be required at each digital input/output. design pcbs thoughtfully once the system's critical paths and circuits have been identified, the next step in implementing sound pcb layout is to partition the printed circuit board according to circuit function. this involves the appropriate use of power, ground, and signal planes. good pcb layouts also isolate critical analog paths from sources of high interference (i/o lines and connectors, for example). high frequency circuits (analog and digital) should be separated from low frequency ones. furthermore, automatic signal routing cad layout software should be used with extreme caution. critical signal paths should be routed by hand, to avoid undesired coupling and/or emissions. properly designed multilayer pcbs can reduce emi emissions and increase immunity to rf fields, by a factor of 10 or more, compared to double-sided boards. a multilayer board allows a complete layer to be used for the ground plane, whereas the ground plane side of a double-sided board is often disrupted with signal crossovers, etc. if the system has separate analog and digital ground and power planes, the analog ground plane should be underneath the analog power plane, and similarly, the digital ground plane should be underneath the digital power plane. there should be no overlap between analog and digital ground planes, nor analog and digital power planes. designing controlled impedances traces on pcbs a variety of trace geometries are possible with controlled impedance designs, and they may be either integral to or allied to the pcb pattern. in the discussions below, the basic patterns follow those of the ipc, as described in standard 2141 (see reference 16). 9.164

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hardware design techniques 9.6 emi/rfi considerations note that the figures below use the term "ground plane". it should be understood that this plane is in fact a large area, low impedance reference plane. in practice it may actually be either a ground plane or a power plane, both of which are assumed to be at zero ac potential. the first of these is the simple wire-over-a-plane form of transmission line, also called a wire microstrip. a cross-sectional view is shown in figure 9.140. this type of transmission line might be a signal wire used within a breadboard, for example. it is composed simply of a discrete insulated wire spaced a fixed distance over a ground plane. the dielectric would be either the insulation wall of the wire, or a combination of this insulation and air. wire wire d d dielectric dielectric h h ground plane ground plane figure 9.140: a wire microstrip transmission line with defined impedance is formed by an insulated wire spaced from a ground plane the impedance of this line in ohms can be estimated with eq. 9.20. here d is the conductor diameter, h the wire spacing above the plane, and εr the dielectric constant. ( ) =ω oz 60 ε r ln   4h d   . eq. 9.20 for patterns integral to the pcb, there are a variety of geometric models from which to choose, single-ended and differential. these are covered in some detail within ipc standard 2141 (see reference 16), but information on two popular examples is shown here. before beginning any pcb-based transmission line design, it should be understood that there are abundant equations, all claiming to cover such designs. in this context, "which of these are accurate?" is an extremely pertinent question. the unfortunate answer is, none are perfectly so! all of the existing equations are approximations, and thus accurate to varying degrees, depending upon specifics. the best known and most widely quoted equations are those of reference 16, but even these come with application caveats. reference 17 has evaluated the reference 16 equations for various geometric patterns against test pcb samples, finding that predicted accuracy varies according to target impedance. reference 18 also evaluates the reference 16 equations, offering an alternative and even more complex set (see reference 19). the equations quoted below are from reference 16, and are offered here as a starting point for a design, subject to 9.165

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analog-digital conversion further analysis, testing and design verification. the bottom line is, study carefully, and take pcb trace impedance equations with a proper dose of salt. microstrip pcb transmission lines for a simple two-sided pcb design where one side is a ground plane, a signal trace on the other side can be designed for controlled impedance. this geometry is known as a surface microstrip, or more simply, microstrip. a cross-sectional view of a two-layer pcb illustrates this microstrip geometry as shown in figure 9.141. trace trace w ww t t dielectric dielectric h h ground plane ground plane figure 9.141: a microstrip transmission line with defined impedance is formed by a pcb trace of appropriate geometry, spaced from a ground plane for a given pcb laminate and copper weight, note that all parameters will be predetermined except for w, the width of the signal trace. eq. 9.21 can then be used to design a pcb trace to match the impedance required by the circuit. for the signal trace of width w and thickness t, separated by distance h from a ground (or power) plane by a pcb dielectric with dielectric constant εr, the characteristic impedance is: ( ) ω = oz 87 ε r + 1.41 ln    5.98h ( 0.8w t+  )  eq. 9.21 note that in these expressions, measurements are in common dimensions (mils). these transmission lines will have not only a characteristic impedance, but also capacitance. this can be calculated in terms of pf/in as shown in eq. 9.22. ( pf/in ) = oc + ( rε 0.67 [ ( ln 5.98h 0.8w ) 1.41 ]t+ ) eq. 9.22 as an example including these calculations, a 2-layer board might use 20-mil wide (w), 1 ounce (t=1.4) copper traces separated by 10-mil (h) fr-4 (εr = 4.0) dielectric material. the resulting impedance for this microstrip would be about 50 ω. for other standard impedances, for example the 75-ω video standard, adjust "w" to about 8.3 mils. 9.166

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hardware design techniques 9.6 emi/rfi considerations some microstrip guidelines this example touches an interesting and quite handy point. reference 17 discusses a useful guideline pertaining to microstrip pcb impedance. for a case of dielectric constant of 4.0 (fr-4), it turns out that when w/h is 2/1, the resulting impedance will be close to 50 ω (as in the first example, with w=20 mils). careful readers will note that eq. 9.21 predicts zo to be about 46 ω, generally consistent with accuracy quoted in reference 17 (>5%). the ipc microstrip equation is most accurate between 50 and 100 ω, but is substantially less so for lower (or higher) impedances. reference 20 gives tabular results of various pcb industry impedance calculator tools. the propagation delay of the microstrip line can also be calculated, as per eq. 9.23. this is the one-way transit time for a microstrip signal trace. interestingly, for a given geometry model, the delay constant in ns/ft is a function only of the dielectric constant, and not the trace dimensions (see reference 21). note that this is quite a convenient situation. it means that, with a given pcb laminate (and given εr), the propagation delay constant is fixed for various impedance lines. ( ns/ft ) pdt = 1.017 0.475 rε + 0.67 eq. 9.23 this delay constant can also be expressed in terms of ps/in, a form which will be more practical for smaller pcbs. this is: ( ps/in ) pdt = 85 0.475 rε + 0.67 eq. 9.24 thus for an example pcb dielectric constant of 4.0, it can be noted that a microstrip's delay constant is about 1.63 ns/ft, or 136 ps/in. these two additional rules-of-thumb can be useful in designing the timing of signals across pcb trace runs. symmetric stripline pcb transmission lines a method of pcb design preferred from many viewpoints is a multi-layer pcb. this arrangement embeds the signal trace between a power and a ground plane, as shown in the cross-sectional view of figure 9.142. the low-impedance ac-ground planes and the embedded signal trace form a symmetric stripline transmission line. as can be noted from the figure, the return current path for a high frequency signal trace is located directly above and below the signal trace on the ground/power planes. the high frequency signal is thus contained entirely inside the pcb, minimizing emissions, and providing natural shielding against incoming spurious signals. 9.167

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hardware design techniques 9.6 emi/rfi considerations some pros and cons of embedding traces the above discussions allow the design of pcb traces of defined impedance, either on a surface layer or embedded between layers. there of course are many other considerations beyond these impedance issues. embedded signals do have one major and obvious disadvantage— the debugging of the hidden circuit traces is difficult to impossible. some of the pros and cons of embedded signal traces are summarized in figure 9.143. not embedded not embedded embedded embedded route route power power ground ground route route power power route route route route ground ground (cid:139) advantages (cid:139) advantages (cid:122) signal traces shielded and protected (cid:122) signal traces shielded and protected (cid:122) lower impedance, thus lower emissions and crosstalk (cid:122) lower impedance, thus lower emissions and crosstalk (cid:122) significant improvement > 50mhz (cid:122) significant improvement > 50mhz (cid:139) disadvantages (cid:139) disadvantages (cid:122) difficult prototyping and troubleshooting (cid:122) difficult prototyping and troubleshooting (cid:122) decoupling may be more difficult (cid:122) decoupling may be more difficult (cid:122) impedance may be too low for easy matching (cid:122) impedance may be too low for easy matching figure 9.143: the pros and cons of not embedding vs. the embedding of signal traces in multi-layer pcb designs multi-layer pcbs can be designed without the use of embedded traces, as is shown in the left-most cross-sectional example. this embedded case could be considered as a doubled two-layer pcb design (i.e., four copper layers overall). the routed traces at the top form a microstrip with the power plane, while the traces at the bottom form a microstrip with the ground plane. in this example, the signal traces of both outer layers are readily accessible for measurement and troubleshooting purposes. but, the arrangement does nothing to take advantage of the shielding properties of the planes. this non embedded arrangement will have greater emissions and susceptibility to external signals, vis-a-vis the embedded case at the right, which uses the embedding, and does take full advantage of the planes. as in many other engineering efforts, the decision of embedded vs. not-embedded for the pcb design becomes a tradeoff, in this case one of reduced emissions vs. ease of testing. dealing with high-speed logic much has been written about terminating pcb traces in their characteristic impedance, to avoid signal reflections. a good guideline to determine when this is necessary is as follows: terminate the transmission line in its characteristic impedance when the one- way propagation delay of the pcb track is equal to or greater than one-half the applied 9.169

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analog-digital conversion signal rise/fall time (whichever edge is faster). for example, a 2 inch microstrip line over an er = 4.0 dielectric would have a delay of ~270 ps. using the above rule strictly, termination would be appropriate whenever the signal rise time is < ~500 ps. a more conservative rule is to use a 2 inch (pcb track length)/nanosecond (rise/fall time) rule. if the signal trace exceeds this trace-length/speed criterion, then termination should be used. for example, pcb tracks for high-speed logic with rise/fall time of 5 ns should be terminated in their characteristic impedance if the track length is equal to or greater than 10 inches (where measured length includes meanders). as an example of what can be expected today in modern systems, figure 9.143 shows typical rise/fall times for several logic families including the sharc dsps operating on +3.3v supplies. as would be expected, the rise/fall times are a function of load capacitance. (cid:139) gaas: 0.1ns (cid:139) ecl: 0.75ns (cid:139) adi sharc dsps: 0.5 ns to 1 ns (operating on +3.3v supply) adsp-21060l sharc: figure 9.143: typical dsp output rise times and fall times in the analog domain, it is important to note that this same 2 inch/nanosecond guideline should also be used with op amps and other circuits, to determine the need for transmission line techniques. for instance, if an amplifier must output a maximum frequency of fmax, then the equivalent risetime tr is related to this fmax. this limiting risetime, tr, can be calculated as: tr = 0.35/fmax eq. 9.29 the maximum pcb track length is then calculated by multiplying tr by 2 inch/nanosecond. for example, a maximum frequency of 100 mhz corresponds to a risetime of 3.5 ns, so a 7-inch or more track carrying this signal should be treated as a transmission line. 9.170

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hardware design techniques 9.6 emi/rfi considerations the best ways to keep sensitive analog circuits from being affected by fast logic are to physically separate the two by the pcb layout, and to use no faster logic family than is dictated by system requirements. in some cases, this may require the use of several logic families in a system. an alternative is to use series resistance or ferrite beads to slow down the logic transitions where highest speed isn't required. figure 9.145 shows two methods. logic gate logic gate logic gate < 2 inches r cin risetime = 2.2 r·cin > 2 inches r c logic gate cin risetime = 2.2 r·(c + cin) figure 9.145: damping resistors slow down fast logic edges to minimize emi/rfi problems in the first, the series resistance and the input capacitance of the gate form a lowpass filter. typical cmos input capacitance is 5 pf to10 pf. locate the series resistor close to the driving gate. the resistor minimizes transient currents and may eliminate the necessity of using transmission line techniques. the value of the resistor should be chosen such that the rise and fall times at the receiving gate are fast enough to meet system requirement, but no faster. also, make sure that the resistor is not so large that the logic levels at the receiver are out of specification because of the voltage drop caused by the source and sink current which flow through the resistor. the second method is suitable for longer distances (>2 inches), where additional capacitance is added to slow down the edge speed. notice that either one of these techniques increases delay and increases the rise/fall time of the original signal. this must be considered with respect to the overall timing budget, and the additional delay may not be acceptable. figure 9.146 shows a situation where several dsps must connect to a single point, as would be the case when using read or write strobes bidirectionally connected from several dsps. small damping resistors shown in figure 9.146a can minimize ringing provided the length of separation is less than about 2 inches. this method will also increase rise/fall times and propagation delay. if two groups of processors must be connected, a single resistor between the pairs of processors as shown in figure 9.146b can serve to damp out ringing. 9.171

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analog-digital conversion a star connection damping resistors sharc dsp use for rd, wr strobes note: these techniques increase rise/fall times and propagation delay b single dampling resistor between processor groups sharc dsp sharc dsp sharc dsp <2" 10ω each <2" 20ω sharc dsp sharc dsp sharc dsp sharc dsp figure 9.146: series damping resistors for high speed dsp interconnections the only way to preserve 1-ns or less rise/fall times over distances greater than about 2 inches without ringing is to use transmission line techniques. figure 9.147 shows two popular methods of termination: end termination, and source termination. the end termination method (figure 9.147a) terminates the cable at its terminating point in the characteristic impedance of the microstrip transmission line. although higher impedances can be used, 50 ω is popular because it minimizes the effects of the termination impedance mismatch due to the input capacitance of the terminating gate (usually 5 pf to 10 pf). in figure 9.147a, the cable is terminated in a thevenin impedance of 50 ω terminated to +1.4 v (the midpoint of the input logic threshold of 0.8 v and 2.0 v). this requires two resistors (91 ω and 120 ω), which add about 50 mw to the total quiescent power dissipation to the circuit. figure 9.147a also shows the resistor values for terminating with a +5v supply (68 ω and 180 ω). note that 3.3-v logic is much more desirable in line driver applications because of its symmetrical voltage swing, faster speed, and lower power. drivers are available with less than 0.5-ns time skew, source and sink current capability greater than 25 ma, and rise/fall times of about 1 ns. switching noise generated by 3.3-v logic is generally less than 5-v logic because of the reduced signal swings and lower transient currents. 9.172

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typical drivers: (cid:132) 74fct3807/a (idt) (cid:132) 74actq240 (fairchild) a zo = 50ω +1.4v hardware design techniques 9.6 emi/rfi considerations +3.3v 120ω 30mw 91ω 22mw +5.0v 180ω 72mw 68ω 29mw +1.4v ground plane end termination b zo ≈ 10ω source termination 39ω zo = 50ω rule of thumb: use transmission line if distance is more than 2"/ns of logic rise/fall time 50ω pc board transmission line delay ≈ 1ns / 7" figure 9.147: termination techniques for controlled impedance microstrip transmission lines the source termination method, shown in figure 9.147b, absorbs the reflected waveform with an impedance equal to that of the transmission line. this requires about 39 ω in series with the internal output impedance of the driver, which is generally about 10 ω. this technique requires that the end of the transmission line be terminated in an open circuit, therefore no additional fanout is allowed. the source termination method adds no additional quiescent power dissipation to the circuit. figure 9.148 shows a method for distributing a high speed clock to several devices. the problem with this approach is that there is a small amount of time skew between the clocks because of the propagation delay of the microstrip line (approximately 1 ns /7"). this time skew may be critical in some applications. it is important to keep the stub length to each device less than 0.5" in order to prevent mismatches along the transmission line. the clock distribution method shown in figure 9.149 minimizes the clock skew to the receiving devices by using source terminations and making certain the length of each microstrip line is equal. there is no extra quiescent power dissipation as would be the case using end termination resistors. figure 9.150 shows how source terminations can be used in bi-directional link port transmissions between sharc dsps. the output impedance of the sharc driver is approximately 17 ω, and therefore a 33-ω series resistor is required on each end of the transmission line for proper source termination. 9.173

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analog-digital conversion and receiver configuration is shown in figure 9.152. the driver consists of a nominal 3.5-ma current source with polarity switching provided by pmos and nmos transistors as in the case of the ad9430 12-bit, 170-/210-msps adc. the output voltage of the driver is nominally 350 mv peak-to-peak at each output, and can vary between 247 mv and 454 mv. the output current can vary between 2.47 ma and 4.54 ma. the lvds receiver is terminated in a 100 ω line-to-line. according to the lvds specification, the receiver must respond to signals as small as 100 mv, over a common-mode voltage range of 50 mv to +2.35 v. the wide common-mode receiver voltage range is to accommodate ground voltage differences up to ±1 v between the driver and receiver. ad9430 output driver ad9430 output driver (+3.3v) (3.5ma) (3.5ma) v+ v– v– v+ +1.2v +1.2v +1.2v 3.5kω 3.5kω 3.5kω 3.5kω 3.5kω 3.5kω (3.5ma) (3.5ma) figure 9.152: lvds driver and receiver the lvds edge speed is defined as the 20% to 90% rise/fall time (as opposed to 10% to 90% for cmos logic) and specified to be less than < 0.3 tui, where tui is the inverse of the data signaling rate. for a 210 msps sampling rate, tui = 4.76 ns, and the 20% to 80% rise/fall time must be less than 0.3 × 4.76 = 1.43 ns. for the ad9430, the rise/fall time is nominally 0.5 ns. lvds outputs for high-performance adcs should be treated differently than standard lvds outputs used in digital logic. while standard lvds can drive 1 to 10 meters in high-speed digital applications (dependent on data rate), it is not recommended to let a high-performance adc drive that distance. it is recommended to keep the output trace lengths short (< 2 in.), minimizing the opportunity for any noise coupling onto the outputs from the adjacent circuitry, which may get back to the analog inputs. the differential output traces should be routed close together, maximizing common-mode rejection, with the 100 ω termination resistor close to the receiver. users should pay attention to pcb trace lengths to minimize any delay skew. a typical differential microstrip pcb trace cross section is shown in figure 9.153 along with some recommended layout guidelines. 9.176

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analog-digital conversion references: 9.6 emi/rfi considerations 1. tim williams, emc for product designers, 2nd ed., newnes, oxford, 1996, isbn: 0 7506 2466 3. 2. henry ott, noise reduction techniques in electronic systems, 2nd ed., john wiley & sons, new york, 1988, isbn 0-471-85068-3. 3. mark montrose, emc and the printed circuit board, ieee press, 1999, isbn 0-7803-4703-x. 4. ralph morrison, grounding and shielding techniques in instrumentation, 3rd ed., john wiley & sons, new york, 1986, isbn 0-471-83805-5. 5. daryl gerke and william kimmel, "designer’s guide to electromagnetic compatibility," edn, january 20, 1994. 6. designing for emc (workshop notes), kimmel gerke associates, ltd., 1994. 7. daryl gerke and william kimmel, "emi and circuit components," edn, september 1, 2000. 8. alan rich, "understanding interference-type noise," analog dialogue, vol. 16, no. 3, 1982, pp. 16-19 (also available as application note an346). 9. alan rich, "shielding and guarding," analog dialogue, vol. 17, no. 1, 1983, pp. 8-13 (also available as application note an347). 10. james wong, joe buxton, adolfo garcia, james bryant, "filtering and protection against emi/rfi" and "input stage rfi rectification sensitivity", chapter 1, pg. 21-55 of systems application guide, 1993, analog devices, inc., norwood, ma, isbn 0-916550-13-3. 11. adolfo garcia, "emi/rfi considerations", chapter 7, pg 69-88 of high speed design techniques, 1996, analog devices, inc., norwood, ma, 1993, isbn 0-916550-17-6. 12. walt kester, walt jung, chuck kitchen, "preventing rfi rectification", chapter 10, pg 10.39-10.43 of practical design techniques for sensor signal conditioning, analog devices, inc., norwood, ma, 1999, isbn 0-916550-20-6. 13. charles kitchen, lew counts, a designer’s guide to instrumentation amplifiers, analog devices, inc., 2000. 14. b4001 and b4003 common-mode chokes, pulse engineering, inc., 12220 world trade drive, san diego, ca, 92128, 619-674-8100, http://www.pulseeng.com 15. understanding common mode noise, pulse engineering, inc., 12220 world trade drive, san diego, ca, 92128, 619-674-8100, http://www.pulseeng.com 16. standard ipc-2141, "controlled impedance circuit boards and high speed logic design," 1996, institute for interconnection and packaging electronic circuits, 2215 sanders road, northbrook, il, 60062-6135, (847) 509-9700, http://www.ipc.org 17. eric bogatin, "verifying the accuracy of 2d field solvers for characteristic impedance calculation," ansoft seminar, october 11, 2000, http://www.bogatinenterprises.com 18. andrew burkhardt, christopher gregg, alan staniforth, "calculation of pcb track impedance," technical paper s-19-5, presented at the ipc printed circuits expo '99 conference, march 14–18, 1999 9.178

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hardware design techniques 9.7 low voltage logic interfacing section 9.7: low voltage logic interfacing walt kester, ethan bordeax, johannes horvath, catherine redmond, eva murphy for nearly 20 years, the standard vdd for digital circuits was 5 v. this voltage level was used because bipolar transistor technology required 5 v to allow headroom for proper operation. however, in the late 1980s, complimentary metal oxide semiconductor (cmos) became the standard for digital ic design. this process did not necessarily require the same voltage levels as ttl circuits, but the industry adopted the 5-v ttl standard logic threshold levels to maintain backward compatibility with older systems (reference 1). the current revolution in supply voltage reduction has been driven by demand for faster and smaller products at lower costs. this push has caused silicon geometries to drop from 2 µm in the early 1980s to 0.18 µm that is used in today's latest microprocessor and ic designs. as feature sizes have become increasingly smaller, the voltage for optimum device performance has also dropped below the 5-v level. this is illustrated in the current microprocessors for pcs, where the optimum core operating voltage is programmed externally using voltage identification (vid) pins, and can be as low as 1.3 v. the strong interest in lower voltage dsps is clearly visible in the shifting sales percentages for 5-v and 3.3-v parts. sales growth for 3.3-v dsps has increased at more than twice the rate of the rest of the dsp market (30% for all dsps versus more than 70% for 3.3-v devices). this trend will continue as the high volume/high growth portable markets demand signal processors that contain all of the traits of the lower voltage dsps. on the one hand, the lower voltage ics operate at lower power, allow smaller chip areas, and higher speeds. on the other hand, the lower voltage ics must often interface to other ics which operate at larger vdd supply voltages thereby causing interface compatibility problems. although lower operating voltages mean smaller signal swings, and hence less switching noise, noise margins are lower for low supply voltage ics. a summary of key points relating to low voltage logic is summarized in figure 9.154. the popularity of 2.5-v devices can be partially explained by their ability to operate from two aa alkaline cells. figure 9.155 shows the typical discharge characteristics for a aa cell under various load conditions (reference 2). note that at a load current of 15 ma, the voltage remains above +1.25 v (2.5 v for two cells in series) for nearly 100 hours. therefore, an ic that can operate effectively at low currents with a supply voltage of 2.5 v ±10% (2.25 v - 2.75 v) is very useful in portable designs. 9.181

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hardware design techniques 9.7 low voltage logic interfacing vdd vdd vdd vih min vil max 0v high = “1” input predriver logic low = “0” vdd voh min pmos high = “1” output nmos low = “0” vol max 0v vil max = maximum allowable input low logic level vih min = minimum allowable input high logic level vol max = maximum allowable output low logic level voh min = minimum allowable output high logic level figure 9.156: typical cmos ic output driver configuration note that the output driver stage consists of a pmos and an nmos transistor. when the output is high, the pmos transistor connects the output to the +vdd supply through its low on-resistance (ron), and the nmos transistor is off. when the output is low, the nmos transistor connects the output to ground through its on-resistance, and the pmos transistor is off. the ron of a cmos output stage can vary between 5 ω and 50 ω depending on the size of the transistors, which in turn, determines the output current drive capability. a typical logic ic has its power supplies and grounds separated between the output drivers and the rest of the circuitry (including the pre-driver). this is done to maintain a clean power supply, which reduces the effect of noise and ground bounce on the i/o levels. this is increasingly important, since added tolerance and compliance are critical in i/o driver specifications, especially at low voltages. figure 9.156 also shows "bars" which define the minimum and maximum required input and output voltages to produce a valid high or low logic level. note that for cmos logic, the actual output logic levels are determined by the drive current and the ron of the transistors. for light loads, the output logic levels are very close to 0 v and +vdd. the input logic thresholds, on the other hand, are determined by the input circuit of the ic. there are three sections in the "input" bar. the bottom section shows the input range that is interpreted as a logic low. in the case of 5-v ttl, this range would be between 0 v and 0.8 v. the middle section shows the input voltage range where it is interpreted as neither a logic low nor a logic high. the upper section shows where an input is interpreted as a logic high. in the case of 5-v ttl, this would be between 2 v and 5 v. similarly, there are three sections in the "output" bar. the bottom range shows the allowable voltage for a logic low output. in the case of 5-v ttl, the ic must output a voltage between 0 v and 0.4 v. the middle section shows the voltage range that is not a 9.183

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analog-digital conversion valid high or low—the device should never transmit a voltage level in this region except when transitioning from one level to the other. the upper section shows the allowable voltage range for a logic high output signal. for 5-v ttl, this voltage is between 2.4 v and 5 v. the chart does not reflect a 10% overshoot/undershoot also allowed on the inputs of the logic standard. a summary of the existing logic standards using these definitions is shown in figure 9.157. note that the input thresholds of classic cmos logic (series-4000, for example) are defined as 0.3 vdd and 0.7 vdd. however, most cmos logic circuits in use today are compatible with ttl and lvttl levels which are the dominant 5-v and 3.3-v operating standards for dsps. note that 5-v ttl and 3.3-v lvttl input and output threshold voltages are identical. the difference is the upper range for the allowable high levels. 5v cmos vcc = 4.5v-5.5v ttl vcc = 4.5v-5.5v voh = 4.44v vih = 0.7 vcc modern 5v or 3.3vcmos logic ics are ttl or lvttl compatible lvttl vcc = 2.7v-3.6v eia/jedec 8-5 2.5v vcc = 2.3v-2.7v eia/jedec 8-5 vth = 0.5 vcc voh = 2.4v voh = 2.4v vil = 0.3 vcc vih = 2.0v vih = 2.0v vth = 1.5v vth = 1.5v vol = 0.5v vil = 0.8v vol = 0.4v vil = 0.8v vol = 0.4v 1.8v vcc = 1.65v-1.95v eia/jedec 8-7 voh = 2.0v vih = 1.7v vil = 0.7v vol = 0.4v voh = vcc – 0.45v vih = 0.65 vcc vil = 0.35 vcc vol = 0.45v figure 9.157: standard logic levels the international standards bureau jedec (joint electron device engineering council) has created a 2.5-v standard (jedec standard 8-5) and a 1.8-v standard (reference 3). there are also a wide range of other low voltage standards, such as gtl (gunning transceiver logic), btl (backplane transceiver logic), ecl (emitter-coupled-logic) pecl (positive ecl logic), and lvds. however, most of these standards are aimed at application specific markets and not for general purpose semiconductor systems. from this chart (figure 9.157), it is possible to visualize some of the possible problems in connecting together two ics operating on different standards. one example would be connecting a 5-v ttl device to a 3.3-v lvttl ic. the 5-v ttl high level is too high for the lvttl to handle ( > 3.3v). this could cause permanent damage to the lvttl chip. another possible problem would be a system with a 2.5-v ic driving a 5-v cmos device. the logic high level from the 2.5-v device is not high enough for it to register as a logic high on the 5-v cmos input (vih min = 3.5 v). these examples illustrate two possible types of logic level incompatibilities—either a device being driven with too high a voltage or a device not driving a voltage high enough for it to register a valid high logic 9.184

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hardware design techniques 9.7 low voltage logic interfacing level with the receiving ic. these interfacing problems introduce two important concepts: voltage tolerance and voltage compliance. voltage tolerance and voltage compliance a device that is voltage tolerant can withstand a voltage greater than its vdd on its i/o pins. for example, if a device has a vdd of 2.5 v and can accept inputs equal to 3.3 v and can withstand 3.3 v on its outputs, the 2.5 v device is called 3.3 v tolerant. the meaning of input voltage tolerance is fairly obvious, but the meaning of output voltage tolerance requires some explanation. the output of a 2.5-v cmos driver in the high state appears like a small resistor (ron of the pmos fet) connected to 2.5 v. obviously, connecting its output directly to 3.3 v is likely to destroy the device due to excessive current. however, if the 2.5-v device has a three-state output which is connected to a bus which is also driven by a 3.3-v ic, then the meaning becomes clearer. even though the 2.5-v ic is in the off (third-state) condition, the 3.3-v ic can drive the bus voltage higher than 2.5 v, potentially causing damage to the 2.5-v ic output. a device which is voltage compliant can receive signals from and transmit signals to a device which is operated at a voltage greater than its own vdd. for example, if a device has a 2.5-v vdd and can transmit and receive signals to and from a 3.3-v device, the 2.5- v device is said to be 3.3-v compliant. the interface between the 5-v cmos and 3.3-v lvttl parts illustrates a lack of voltage tolerance; the lvttl ic input is overdriven by the 5-v cmos device output. the interface between the 2.5-v jedec and the 5-v cmos part demonstrates a lack of voltage compliance; the output high level of the jedec ic does not comply to the input level requirement of a the 5-v cmos device. the definitions of voltage compliance and voltage tolerance are repeated in figure 9.158. (cid:139) voltage tolerance: (cid:122) a device that is voltage tolerant can withstand a voltage greater than its vdd on its input and output pins. if a device has a vdd of 2.5v and can accept inputs of 3.3v (±10%), the 2.5v device is 3.3v tolerant on its input. input and output tolerance should be examined and specified separately. (cid:139) voltage compliance: (cid:122) a device that is voltage compliant can transmit and receive signals to and from logic which is operated at a voltage greater than its own vdd. if a device has a 2.5v vdd and can properly transmit signals to and from 3.3v logic, the 2.5v device is 3.3v compliant. input and output compliance should be examined and specified separately. figure 9.158: logic voltage tolerance and compatibility definitions 9.185

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analog-digital conversion interfacing 5v systems to 3.3v systems using nmos fet "bus switches" when combining ics that operate on different voltage standards, one is often forced to add additional discrete elements to ensure voltage tolerance and compliance. in order to achieve voltage tolerance between 5-v and 3.3-v logic, for instance, a bus switch voltage translator such as the adg3257 can be used (also see references 4, 5). the bus switch limits the voltage applied to an ic. this is done to avoid applying a larger input high voltage than the receiving device can tolerate. as an example, it is possible to place a bus switch between a 5-v cmos and 3.3-v lvttl ic, and the two devices can then transmit data properly as shown in figure 9.159. the bus switch is basically an nmos fet. if 4.3 v is placed on the gate of the fet, the maximum passable signal is 3.3 v (approximately 1 v less than the gate voltage). if both input and output are below 3.3 v, the nmos fet acts as a low resistance (ron ≈ 2 ω). as the input approaches 3.3 v, the fet on-resistance increases, thereby limiting the signal output. the adg3257 is a quad 2:1 mux/demux bus switch with a gate drive enable as shown in the lower half of figure 9.159. the vcc of the adg3257 sets the high level for the gate drive. + 3.3v bus + 5v bus vcc = + 4.3v ≈ 0.7v 0.1µf 3.3v logic nmos 5v logic ron = 2 ω 0v / vcc adg3257 quad 2:1 mux/demux bus switch, 1na typical current operate with vcc = +4.3v for 5v/3.3v and vcc = +3.3v for 3.3v/2.5v "1" = disable "0" = enable figure 9.159: +5 v/+3.3 v bidirectional interface using nmos fet achieves voltage tolerance one way of creating a 4.3-v supply on a 5-v/3.3-v system board is to simply place a silicon diode between the 5-v supply and vcc on the bus switch as shown in figure 9.159. for 3.3 v/2.5 v applications, the vcc pin can be connected directly to the +3.3-v supply. some bus switches are designed to operate on either 3.3 v or 5 v directly and generate the internal gate bias level internally. 9.186

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hardware design techniques 9.7 low voltage logic interfacing a bus switch removes voltage tolerance concerns in this mixed logic design. one convenient feature of bus switches is that they are bi-directional; this allows the designer to place a bus translator between two ics and not have to create additional routing logic for input and output signals. a bus switch increases the total power dissipation along with the total area required to layout a system. since voltage bus switches are typically cmos circuits, they have very low power dissipation ratings. an average value for added continuous power dissipation is 5 mw per package (10 switches), and this is independent of the frequency of signals which pass through the circuit. bus switches typically have 8 - 20 i/o pins per package and take up approximately 25 to 50 mm2 of board space. one concern when adding interface logic into a circuit is a possible increase in propagation delay. added propagation delay can create many timing problems in a design. bus switches have very low propagation delay values. the bus switch contributes practically no propagation delay (0.1 ns typical for the adg3257) other than the rc delay of the typical ron of the switch and the load capacitance when driven by an ideal voltage source. since the time constant is typically much smaller than the rise/fall times of typical driving signals, bus switches add very little propagation delay to the system. low ron is therefore critical for bus switches, since the switch on-resistance in conjunction with the bus capacitance creates a single- pole filter which can add delay and reduce the maximum data rate. the typical on- capacitance of the adg3257 is 10 pf, and this capacitance in conjunction with an ron of 4 ω yields a rise/fall time of approximately 90 ps. figure 9.160 shows the adg3257 on- resistance as a function of input voltage for 5.5-, 5-, 4.5-, 3.3-, 3.0-, and 2.7-v supplies. maximum pass voltage as a function of input voltage is shown in figure 9.161. vin (v) vin (v) figure 9.160: on resistance vs. input voltage for adg3257 bus switch 9.187

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analog-digital conversion device or a number of devices, thus allowing easy bypassing of one or more devices in a chain. this may be particularly useful in reducing the time overhead in testing devices in the jtag chain or in daisy-chain applications where the user does not wish to change the settings of a particular device. the bypass switch is packaged in two of the smallest footprints available for its required pin count. the 8-lead sot-23 package requires only 8.26 mm × 8.26 mm board space, while the msop package occupies approximately 15 mm × 15 mm board area. a functional block diagram of the adg3233 is shown in figure 9.167. figure 9.167: adg3233 low voltage 1.65-v to 3.6-v, logic level translator and bypass switch figure 9.168 shows the bypass switch being used in normal mode. in this mode, the signal paths are from a1 to y1 and a2 to y2. the device will level translate the signal applied to a1 to a vcc1 logic level (this level translation can be either to a higher or lower supply) and route the signal to the y1 output, which will have standard vol/voh levels for vcc1 supplies. the signal is then passed through device 1 and back to the a2 input pin of the bypass switch. the logic level inputs of a2 are with respect to the vcc1 supply. the signal will be level translated from vcc1 to vcc2 and routed to the y2 output pin of the bypass switch. y2 output logic levels are with respect to the vcc2 supply. figure 9.169 illustrates the device as used in bypass operation. the signal path is now from a1 directly to y2, thus bypassing device 1 completely. the signal will be level translated to a vcc2 logic level and available on y2, where it may be applied directly to the input of device 2. in bypass mode, y1 is pulled up to vcc1. the three supplies in figures 9.168 and 9.169 may be any combination of supplies, i.e., vcc0, vcc1, and vcc2 may be any combination of supplies, for example, 1.8 v, 2.5 v, and 3.3 v. 9.192

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hardware design techniques 9.7 low voltage logic interfacing internally created voltage tolerance / compliance modern high performance cmos dsps and microprocessors typically operate on core voltages between 1 v and 2 v. these low voltages yield optimum speed-power performance. however, the logic levels in the core are not compatible with standard 2.5-v or 3.3-v i/o interfaces. this problem is typically solved as shown in figure 9.172, where the logic core operates at a reduced voltage, but the output drivers operate at a standard supply voltage level of 2.5 v or 3.3 v. vdd internal(core) vdd external secondary i/o ring input core logic pmos nmos output internal gnd external gnd vdd external = +2.5v or +3.3v vdd core = +0.9v to +1.8v (depending on processor) input +2.5v or +3.3v tolerant figure 9.172: internal compliance and tolerance in a cmos ic with secondary i/o ring the technique followed by many ic manufacturers is to provide a secondary i/o ring, i.e., the i/o drivers are driven by the 2.5-v or 3.3-v power supply, hence the device is compatible with 2.5-v or 3.3-v logic levels. note that the inputs must be compliant and tolerant to the i/o supply voltage. there are several issues to consider in a dual-supply logic ic design of this type: • power-up sequencing: if two power supplies are required to give an ic additional tolerance / compliance, what is the power-up sequence? is it a requirement that the power supplies are switched on simultaneously or can the device only have a voltage supplied on the core or only on the i/o ring? this problem can be easily solved if the core voltage is generated from the i/o supply voltage using a low dropout linear regulator. • process support and electro-static discharge (esd) protection: the transistors created in the ic's fabrication process must be able to both withstand and drive high voltages. the high voltage transistors create additional fabrication costs since they require more processing steps to build in high voltage tolerance. designs with standard transistors require additional circuitry. the i/o drivers must also provide 9.195

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hardware design techniques 9.8 breadboarding and prototyping section 9.8: breadboarding and prototyping walt kester, james bryant, walt jung a basic principle of a breadboard or a prototype structure is that it is a temporary one, designed to test the performance of an electronic circuit or system. by definition it must therefore be easy to modify, particularly so for a breadboard. there are many commercial prototyping systems, but unfortunately for the analog designer, almost all of them are designed for prototyping digital systems. in such environments, noise immunities are hundreds of millivolts or more. prototyping methods commonly used include non copper-clad matrix board, vectorboard, wire-wrap, and plug-in breadboard systems. quite simply, these all are unsuitable for high performance or high frequency analog prototyping, because of their excessively high parasitic resistance, inductance, and capacitance levels. even the use of standard ic sockets is inadvisable in many prototyping applications (more on this, below). (cid:139) always use a large area ground plane for precision or high frequency circuits (cid:139) minimize parasitic resistance, capacitance, and inductance (cid:139) if sockets are required, use "pin sockets" ("cage jacks") (cid:139) pay equal attention to signal routing, component placement, grounding, and decoupling in both the prototype and the final design (cid:139) popular prototyping techniques: (cid:122) freehand "deadbug" using point-to-point wiring (cid:122) "solder-mount" (cid:122) milled pc board from cad layout (cid:122) multilayer boards: double-sided with additional point- to-point wiring (cid:122) modern surface-mount ics in small packages require special techniques—usually a preliminary multilayer pc board layout figure 9.173: a summary of analog prototyping system key points figure 9.173 summarizes a number of key points on selecting a useful analog breadboard and/or prototyping system, which are further discussed below. one of the more important considerations in selecting a prototyping method is the requirement for a large-area ground plane. this is required for high frequency circuits as well as low speed precision circuits, especially when prototyping circuits involving adcs or dacs. the differentiation between high-speed and high-precision mixed-signal circuits is difficult to make. for example, 16+ bit adcs (and dacs) may operate on high speed clocks (>10 mhz) with rise and fall times of less than a few nanoseconds, while the effective throughput rate of the converters may be less than 100 ksps. successful 9.199

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analog-digital conversion prototyping of these circuits requires that equal (and thorough) attention be given to good high-speed and high-precision circuit techniques. several years ago, many ics were offered in both dip and surface-mount packages, so breadboarding and prototyping could be done using the user-friendly dip package. today, however, most high-performance data converters are not available in dip packages—and if they were, the added package parasitics would limit performance in many cases. breadboarding and prototyping in today's environment is especially difficult, because modern surface-mounted ics in small packages can be extremely difficult to solder into any type of pc board using manual techniques. ball grid array (bga) packages are nearly impossible to solder manually. sockets—very expensive if available—are generally out of the question because of added parasitics, so in many cases, an actual multilayer pc board must be designed and fabricated. this trend has placed an even greater responsibility on the ic manufacturer to supply a variety of high quality well documented evaluation boards to assist in the initial design phases of a project. "deadbug" prototyping a simple technique for analog prototyping where dip ics are available uses a solid copper-clad board as a ground plane (see references 1 and 2). in this method, the ground pins of the ics are soldered directly to the plane, and the other components are wired together above it. this allows hf decoupling paths to be very short indeed. all lead lengths should be as short as possible, and signal routing should separate high-level and low-level signals. connection wires should be located close to the surface of the board to minimize the possibility of stray inductive coupling. in most cases, 18-gauge or larger insulated wire should be used. parallel runs should not be "bundled" because of possible coupling. ideally the layout (at least the relative placement of the components on the board) should be similar to the layout to be used on the final pcb. this approach is often referred to as deadbug prototyping, because the ics are often mounted upside down with their leads up in the air (with the exception of the ground pins, which are bent over and soldered directly to the ground plane). the upside-down ics look like deceased insects, hence the name. figure 9.174 shows a hand-wired "deadbug" analog breadboard. this circuit uses two high speed op amps, and in fact gives excellent performance in spite of its lack of esthetic appeal. the ic op amps are mounted upside down on the copper board with the leads bent over. the signals are connected with short point-to-point wiring. the characteristic impedance of a wire over a ground plane is about 120 ω, although this may vary as much as ±40% depending on the distance from the plane. the decoupling capacitors are connected directly from the op amp power pins to the copper-clad ground plane. when working at frequencies of several hundred mhz, it is a good idea to use only one side of the board for ground. many people drill holes in the board and connect the sides together by soldering short pieces of wire. if care isn’t taken, this may result in unexpected ground loops between the two sides of the board, especially at rf frequencies. 9.200

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hardware design techniques 9.8 breadboarding and prototyping figure 9.174: a "deadbug" analog breadboard pieces of copper-clad board may be soldered at right angles to the main ground plane to provide screening, or circuitry may be constructed on both sides of the board (with through-hole connections) with the board itself providing screening. for this, the board will need corner standoffs to protect underside components from being crushed. when the components of a breadboard of this type are wired point-to-point in the air (a type of construction strongly advocated by bob pease (see reference 2) and sometimes known as "bird's nest" construction) there is always the risk of the circuitry being crushed and resulting short-circuits. also, if the circuitry rises high above the ground plane, the screening effect of the ground plane is diminished, and interaction between different parts of the circuit is more likely. nevertheless, the technique is very practical and widely used because the circuit may easily be modified (this of course assumes the person doing the modifications is adept with soldering techniques). another prototype breadboard variation is shown in figure 9.175. here the single-sided copper-clad board has pre-drilled holes on 0.1" centers (see reference 3). power busses are used at the top and bottom of the board. the decoupling capacitors are used on the power pins of each ic. because of the loss of copper area due to the pre-drilled holes, this technique does not provide as low a ground impedance as a completely covered copper- clad board of figure 9.174, so be forewarned. in a variation of this technique, the ics and other components are mounted on the non- copper-clad side of the board. the holes are used as vias, and the point-to-point wiring is done on the copper-clad side of the board. note that the copper surrounding each hole used for a via must be drilled out, to prevent shorting. this approach requires that all ic 9.201

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analog-digital conversion pins be on 0.1" centers. for low frequency circuits, low profile sockets can be used, and the socket pins then will allow easy point-to-point wiring. figure 9.175: "a deadbug" prototype using 0.1" pre-drilled single-sided, copper-clad printed board material solder-mount prototyping there is a commercial breadboarding system which has most of the advantages of the above techniques (robust ground, screening, ease of circuit alteration, low capacitance and low inductance) and several additional advantages: it is rigid, components are close to the ground plane, and where necessary, node capacitances and line impedances can be calculated easily. this system is made by wainwright instruments and is available in europe as "mini-mount" and in the usa (where the trademark "mini-mount" is the property of another company) as "solder-mount" (see references 4 and 5). solder-mount consists of small pieces of pcb with etched patterns on one side and contact adhesive on the other. these pieces are stuck to the ground plane, and components are soldered to them. they are available in a wide variety of patterns, including ready-made pads for ic packages of all sizes from 8-pin soics to 64-pin dils, strips with solder pads at intervals (which intervals range from 0.040" to 0.25", the range includes strips with 0.1" pad spacing which may be used to mount dil devices), strips with conductors of the correct width to form microstrip transmission lines (50 ω, 60 ω, 75 ω or 100 ω) when mounted on the ground plane, and a variety of pads for mounting various other components. self-adhesive tinned copper strips and rectangles (lo-pads) are also available as tie-points for connections. they have a relatively high capacitance to ground and therefore serve as low-inductance decoupling capacitors. they come in sheet form and may be cut with a knife or scissors. the main advantage of solder-mount construction over "bird's nest" or "deadbug" is that the resulting circuit is far more rigid, and, if desired, may be made far smaller (the latest solder-mounts are for surface-mount devices and allow the construction of breadboards scarcely larger than the final pcb, although it is generally more convenient if the prototype is somewhat larger). solder-mount is sufficiently durable that it may be used for small quantity production as well as prototyping. 9.202

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hardware design techniques 9.8 breadboarding and prototyping figure 9.176 shows an example of a 2.5-ghz phase-locked-loop prototype, built with solder-mount techniques. while this is a high speed circuit, the method is equally suitable for the construction of high resolution low frequency analog circuitry. figure 9.176: a "solder-mount" constructed prototype board a particularly convenient feature of solder-mount at vhf is the relative ease with which transmission lines can be formed. as noted earlier, if a conductor runs over a ground plane, it forms a microstrip transmission line. the solder-mount components include strips which form microstrip lines when mounted on a ground plane (they are available with impedances of 50 ω, 60 ω, 75 ω, and 100 ω). these strips may be used as transmission lines for impedance matching, or alternately, more simply as power buses. note that glass fiber/epoxy pcb is somewhat lossy at vhf/ uhf, but losses will probably be tolerable if microstrip runs are short. milled pcb prototyping both "deadbug" and "solder-mount" prototypes become tedious for complex analog circuits, and larger circuits are better prototyped using more formal layout techniques. there is a prototyping approach that is but one step removed from conventional pcb construction, described as follows. this is to actually lay out a double-sided board, using conventional cad techniques. pc-based software layout packages offer ease of layout as well as schematic capture to verify connections (see references 6 and 7). although most layout software has some degree of auto-routing capability, this feature is best left to digital designs. the analog traces and component placements should be done by hand, following the rules discussed elsewhere in this chapter. after the board layout is complete, the software verifies the connections per the schematic diagram net list. 9.203

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analog-digital conversion many designers find that they can make use of cad techniques to lay out simple boards. the result is a pattern-generation tape (or gerber file) which would normally be sent to a pcb manufacturing facility where the final board is made. rather than use a pcb manufacturer, however, automatic drilling and milling machines are available which accept the pg tape directly (see references 8 and 9). an example of such a prototype circuit board is shown in figure 9.177 (top view). figure 9.177: a milled circuit construction prototype board (top view) these systems produce either single or double-sided circuit boards directly, by drilling all holes and using a milling technique to remove conductive copper, thus creating the required insulation paths, and finally, the finished prototype circuit board. the result can be a board functionally quite similar to a final manufactured double-sided pcb. however, it should be noted that a chief caveat of this method is that there is no "plated- through" hole capability. because of this, any conductive "vias" required between the two layers of the board must be manually wired and soldered on both sides. minimum trace widths of 25 mils (1 mil = 0.001") and 12 mil spacing between traces are standard, although smaller trace widths can be achieved with care. the minimum spacing between lines is dictated by the size of the milling bit used, typically 10 to 12 mils. a bottom-side view of this same milled prototype circuit board is shown in figure 9.178. the accessible nature of the copper pattern allows access to the traces for modifications. perhaps the greatest single advantage of the milled circuit type of prototype circuit board is that it approaches the format of the final pcb design most closely. by its very nature 9.204

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analog-digital conversion to use this technique, clear the copper (on both sides of the board) for about 0.5-mm around each ungrounded pin socket, then solder the grounded socket pins to ground, on both sides of the board. both capped and uncapped versions of these pin sockets are available (amp part numbers 5-330808-3, and 5-330808-6, respectively). the pin sockets protrude through the board far enough to allow point-to-point wiring interconnections. because of the spring-loaded gold-plated contacts within the pin socket, there is good electrical and mechanical connection to the ic pins. multiple insertions, however, may degrade the performance of the pin socket, so this factor should be kept in mind. note also that the uncapped versions allow the ic pins to extend out the bottom of the socket. this feature leads to an additional useful function. once a prototype using the pin sockets is working and no further changes are to be made the ic pins can be soldered directly to the bottom of the socket. this establishes a rugged, permanent connection. some additional prototyping points the prototyping techniques discussed so far have been limited to single or double-sided pcbs. multilayer pcbs do not easily lend themselves to standard prototyping techniques. if multilayer board prototyping is required, one side of a double-sided board can be used for ground and the other side for power and signals. point-to-point wiring can be used for additional runs which would normally be placed on the additional layers provided by a multi-layer board. however, it is difficult to control the impedance of the point-to-point wiring runs, and the high frequency performance of a circuit prototyped in this manner may differ significantly from the final multilayer board. other difficulties in prototyping may occur with op amps or other linear devices having bandwidths greater than a few hundred megahertz. small variations in parasitic capacitance (< 1 pf) between the prototype and the final board can cause subtle differences in bandwidth and settling time. sometimes, prototyping is done with dip packages (if available), when the final production package is an soic. this is not recommended! at high frequencies, small package-related parasitic differences can account for different performance, between prototype and final pcb. to minimize this effect, always prototype with the final packages. evaluation boards most manufacturers of analog ics provide evaluation boards usually at a nominal cost. these boards allow customers to evaluate ics without constructing their own prototypes. regardless of the product, the manufacturer has taken proper precautions regarding grounding, layout, and decoupling to ensure optimum device performance. where applicable, the evaluation pcb artwork is usually made available free of charge, should a customer wish to copy the layout directly or make modifications to suit an application. 9.206

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hardware design techniques 9.8 breadboarding and prototyping general purpose op amp evaluation board from the mid-1990s evaluation boards can be either dedicated to a particular ic, or they can also be general purpose. with op amps the most universal linear ic, it is logical that evaluation boards be developed for them, to aid easy applications. however, it is also important that a good quality evaluation board avoid the parasitic effects discussed above. an example is the general purpose dual amplifier evaluation board of in figure 9.190 (see reference 10). figure 9.190: a mid-1990s general purpose op amp evaluation board allowed fast, easy configuration of low frequency op amps in dil packages this board uses pin sockets for any standard dual op amp pinout device, and a flexible set of component jumper locations allows it to be setup for inverting or non-inverting amplifiers. various gains can be configured by choice of the component values, in either ac- or dc-coupled configurations. the card design provides signal coupling via bnc connectors at input and output. it also uses external lab power supplies, which are wired to the lug terminals at the top. the card does however contain local supply voltage decoupling and bypassing components. these general purpose boards are intended for medium to high precision uses at frequencies below 10 mhz, with moderate op amp input currents. for higher operating speeds, a dedicated, device-specific evaluation board is a better choice. dedicated op amp evaluation boards in high speed/high precision ics, special attention must be given to power supply decoupling. for example, fast slewing signals into relatively low impedance loads produce high speed transient currents at the power supply pins of an op amp. the transient currents produce corresponding voltages across any parasitic impedance that may exist in the power supply traces. these voltages, in turn, may couple to the amplifier output, because of the op amp's finite power supply rejection at high frequencies. the ad8001 high speed current-feedback amplifier is a case in point, and a dedicated evaluation board is available for it. a bottom side view of this soic board is shown in 9.207

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analog-digital conversion figure 9.181. a triple decoupling scheme was chosen, to ensure a low impedance ground path at all transient frequencies. highest frequency transients are shunted to ground by dual 1000-pf/0.01-µf ceramic chip capacitors, located as close to the power supply pins as possible to minimize series inductance and resistance. with these surface mount components, there is minimum stray inductance and resistance in the ground plane path. lower frequency transient currents are shunted by the larger 10-µf tantalum capacitors. figure 9.181: a high speed op amp such as the ad8001 requires a dedicated evaluation board with suitable ground planes and decoupling (bottom view) the input and output signal traces of this board are 50-ω microstrip transmission lines, as can be noted towards the right and left. gain-set resistors are chip-style film resistors, which have low parasitic inductance. these can be seen in the center of the photo, mounted at a slight diagonal. note also that there is considerable continuous ground plane area on both sides of the pcb. plated-through holes connect the top and bottom side ground planes at several points, in order to maintain lowest possible impedance and best high frequency ground continuity. input and output connections to the card are provided via the sma connectors as shown, which terminate the input/output signal transmission lines. the board’s power connection from external lab supplies is made via solder terminals, which are seen at the ends of the broad supply line traces. some of these points are more easily seen in a topside view of the same card, which is shown in figure 9.182. this ad8001 evaluation board is a non-inverting signal gain stage, optimized for lowest parasitic capacitance. the cutaway area around the soic outline of the ad8001 provides lowest stray capacitance, as can be noted in this view. 9.208

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hardware design techniques 9.8 breadboarding and prototyping figure 9.182: the ad8001 evaluation board uses a large area ground plane as well as minimal parasitic capacitance (top view) in this view is also seen the virtually continuous ground plane and the multiple vias, connecting the top/bottom planes. data converter evaluation boards a well designed manufacturers' evaluation board is a powerful tool that can greatly simplify the integration of an adc or dac into a system. probably the best feature of an evaluation board is that its layout is designed to optimize the performance of the data converter. analog devices provides a complete electrical schematic and parts list as well as a pc board layout of its evaluation boards on the data sheet for most adcs and dacs. each layer of the multilayer board is also shown, and analog devices will supply the cad layout files (gerber format) for the board if needed. many system level problems related to layout can be avoided simply by studying the evaluation board layout and using it as a guide in the system board layout—perhaps even copying critical parts of the layout directly if needed. evaluation boards typically have input/output connectors for the analog, digital, and power interfaces to facilitate interfacing with external test equipment. any required support circuitry such as voltage references, crystal oscillators for clock generation, etc., are generally included as part of the board. many modern data converters have a considerable amount of on-chip digital logic for controlling various modes of operation, including gain, offset, calibration, data transfer, etc. these options are set by loading the appropriate words into internal control registers, usually via a serial port. in some converters, especially sigma-delta adcs, just setting the basic options requires considerable knowledge of the internal control registers and the interface. for this reason, most adc/dac evaluation boards have interfaces (either parallel, serial, or usb) and software to allow easy menu-driven control of the various internal options from an external pc. in many cases, configuration files created in the evaluation software can be downloaded into the final system design. 9.209

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analog-digital conversion figure 9.183 shows the evaluation board for the ad7730 24-bit bridge transducer sigma- delta adc. this adc has an on-chip pga and is designed to interface directly to a variety of bridge transducers. a load cell with a 10-mv full-scale output can be connected directly to the adc input, and the output is read by the pc via the parallel port interface. the evaluation board software allows the system designer to see the effects of sample rate, gain, filter bandwidth, and output data averaging on the overall effective resolution. the software also provides histogram displays for direct evaluation of system noise. vexc=+5 v vdd=+5 v +5v vref=+5 v ain=10 mv ad7730 hos t system digital adc 2 4-bit calibration sensor evaluation board computer figure 9.183: ad7730 measurement adc evaluation system figure 9.184 shows the evaluation board for the ad5535 32-channel 14-bit high voltage dac. the evaluation board interfaces with an external pc via a parallel port connector. the software provided with the board allows data to be easily loaded into the individual dac registers via the 3-wire serial interface. figure 9.185 shows an adc evaluation board for the ad7450 12-bit 1-msps adc connected to an evaluation/control board. the adc evaluation board (right side of diagram) is product-specific, but the evaluation/control board interfaces to a variety of adc evaluation boards and has an on-board 16-bit buffer memory and control logic which interfaces to a pc via the parallel port. the software provided includes an fft routine which allows evaluating the adc under dynamic conditions. the evaluation/control board can handle adcs with sampling rates up to several mhz. 9.210